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Design of Digital Multiplier with Reversible Logic by Using the Ancient Indian Vedic Mathematics Suitable for Use in Hardware of Cryptosystems

by Giridhari Muduli, Siddharth Kumar Dash, Bibhu Datta Pradhan and Manas Ranjan Jena

International Transaction of Electrical and Computer Engineers System. 2014, 2(4), 114-119. DOI: 10.12691/iteces-2-4-1
Pub. Date: July 20, 2014Views: 36988 Downloads: 31608Like: 36Citations: 1

DPA DA ASIC CMOS SCRL

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