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A Novel Dedicated Low Power 64 Bit Digital Comparator Using Cmos Logic
by Shilparani Panda, Asirbad Behera, Manas Ranjan Jena and Snigdharani Nath
Journal of Embedded Systems. 2014, 2(2), 28-31. DOI: 10.12691/jes-2-2-2
Pub. Date: June 01, 2014Views: 35479Downloads: 32522
Binary comparator digital arithmetic Power delay product (pdp) CMOS logic
Abstract Full Text PDF (324 KB) Full Text HTML Full Text ePUB (488 KB)
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