A High Resolution First Order Noise-Shaping Vernier Time-to-Digital Converter

Majid Memarian Sorkhabi^1, and Siroos Toofan¹

¹Department of Electric Engineering Zanjan University, Iran

Cite this paper:
Majid Memarian Sorkhabi and Siroos Toofan. A High Resolution First Order Noise-Shaping Vernier Time-to-Digital Converter. American Journal of Electrical and Electronic Engineering. 2013; 1(2):19-22. doi: 10.12691/ajeee-1-2-1

Abstract

In this paper, we propose a noise reduction method for a Vernier Time-to-Digital Converter (VTDC) using a first-order noise shaping structure and a gated ring oscillator (GRO). An 11bit VTDC with 4 p s effective resolution was designed and developed for a high performance All Digital Frequency Synthesizer (ADFS). The VTDC realized in 180nm CMOS, its power consumption depending on the time difference between input edges; 1 to 11mA from a 1.5 V supply.

Keywords:
vernier time-to-digital-converter noise shaping ring oscillator

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References:

[1]	B. Helal, Techniques for Low Jitter Clock Multiplication, MIT, Ph.D. thesis, 2008, 100-135.
[2]	C. Hesu, Techniques for High Performance Digital Frequency Synthesis and Phase Control, MIT, Ph.D. thesis, 2008, 61-87.
[3]	M. Straayer, Noise shaping techniques for analog and TDC using voltage controlled oscillator, MIT, Ph.D. thesis, 2008, 124-152.
[4]	K. Ok, A Stochastic Time-to-Digital Converter for Digital Phase-Locked Loops, Oregon State University MSC. Thesis, 2005, 25-46.
[5]	F. Brandonisio and others, “First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter,” IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, 41‐44.
[6]	J. Yu, F. F. Dai and R. Jaeger, “A 12-bit Vernier Ring Time-to-Digital Converter in 130nm Technology '', in IEEE J. of Solid S. Circuits. VOL. 45 NO. 4, 830- 842, Apr. 2010.
[7]	B. Helal, M. Straayer, and M. H. Perrott, “A low jitter 1.6 GHz multiplying DLL utilizing a scrambling time-to-digital converter and digital correlation,” in VLSI Symp. Dig. Tech. Papers, 166–167, Jun. 2007.
[8]	J. Doernberg, H. S. Lee, and D. A. Hodges, “Full-speed testing of A/D converters,” IEEE J. Solid-State Circuits, vol. SC-19, 820–827, Dec. 1984.
[9]	B. Swann, B. Blalock and others, “A 100-ps Time-Resolution CMOS TDC For Position Emission Tomography, ” IEEE J. Solid-State Circuits, vol. 39, NO.11, 1839-1852, Nov.2004.