Design of Digital Multiplier with Reversible Logic by Using the Ancient Indian Vedic Mathematics Suitable for Use in Hardware of Cryptosystems

Giridhari Muduli¹, Siddharth Kumar Dash¹, Bibhu Datta Pradhan¹ and Manas Ranjan Jena^1,

¹Department of ETC, SIET, Dhenkanal, Odisha, India

Cite this paper:
Giridhari Muduli, Siddharth Kumar Dash, Bibhu Datta Pradhan and Manas Ranjan Jena. Design of Digital Multiplier with Reversible Logic by Using the Ancient Indian Vedic Mathematics Suitable for Use in Hardware of Cryptosystems. International Transaction of Electrical and Computer Engineers System. 2014; 2(4):114-119. doi: 10.12691/iteces-2-4-1

Abstract

Differential Power Analysis (DPA) presents a major challenge to mathematically secure cryptographic protocols. Attacks can break the encryption by measuring the energy consumed in the working digital circuit. To prevent this types of attack, this paper proposes the use of reversible logic for designing a high speed complex multiplier (ASIC) based on Vedic mathematics in cryptosystem. Reversible logic is gaining significance in the context of emerging technology such as quantum computing. Ideally, reversible circuits do not loose information during computation. Thus, it would be of great significance to apply reversible logic to design for secure cryptosystem. The idea for designing the multiplier unit is adopted from ancient Indian mathematics “Vedas”. On account of these formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the vedic mathematics & their application to the complex multiplier ensure substantial reduction of propagation delay in comparison with DA based architecture (distributed arithmetic) & parallel adder based implementation which are commonly used. The functionality of these circuits was checked & performance parameters like propagation delay and dynamic power consumption were calculated by spice specter using standard 90nm cmos technology.

Keywords:
DPA DA ASIC CMOS SCRL

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References:

[1]	Bayrakci, A. and Akkas, A.. “Reduced delay bcd adder”, Proc. Application -specic Systems, Architectures and Processors. 266-271, 2007.
[2]	Biswas, A. K., Hasan, M. M., Chowdhury, A. R., and Hasan Babu, H. M. “Efficient approaches for designing reversible binary coded decimal adders”, Microelectron. J. 39, 12, 1693-1703, 2008.
[3]	Bruce, J. W., Thornton, M. A., Shivakumaraiah, L., Kokate, P. S., and Li, X. “Efficient adder circuits based on a conservative reversible logic gate”, Proc. IEEE Symposium on VLSI, 2002. 83-88, 2002.
[4]	Cuccaro, S. A., Draper, T. G., Kutin, S. A., and Moulton, D. P. “A new quantum ripple-carry addition circuit”, http://arXiv.org/quant-ph/0410184,2004.
[5]	Haghparast, M., Jassbi, S., Navi, K., and O.Hashemipour. “Design of a novel reversible multiplier circuit using hng gate in nanotechnology”, World App. Sci. J. 3, 6, 974-978, 2008.
[6]	Maslov, D. and Dueck, G. W. “Reversible cascades with minimal garbage”, IEEE Trans. Computer-Aided Design, 23, 11 (Nov.), 1497-1509, 2004.
[7]	Mohammadi, M., Eshghi, M., Haghparast, M., and Bahrololoom, A. “Design and optimization of reversible bcd adder/subtractor circuit for quantum and nanotechnology based systems”, World Applied Sciences Journal 4, 6, 787-792, 2008..
[8]	Shende, V. V., Prasad, A., Markov, I., and Hayes, J. “Synthesis of reversible logic Circuits”. IEEE Trans. on CAD 22, 710-722, 2003.
[9]	S.K.Sastry, H.S.Shroff, Mahammad, S. N., and Kamakoti, V. “Efficient building blocks for reversible sequential circuit design”. Proc. the 49th IEEE Intl. l Midwest Symp.on Cir. and Sys. Puerto Rico, 437-441, 2006.
[10]	B. Parhami, “Computer architecture arithmetic algorithms & hardware architectures”, 2nd edition, Oxford university press, New York, 2010.
[11]	Anvesh kumar, Ashish raman,”Low power ALU design by ancient mathematics”, 978-1-4244-5586-7/10, 2010, IEEE.