Study of the Power Consumption of a Digital-Front-End Using Random Sampling

Deng Xiaoyu¹, M. Diop^2, and J.F. Diouris¹

¹Ecole polytechnique de l’Université de Nantes, Rue C. Pauc, La Chantrerie, Nantes, France

²Ecole Supérieure Polytechnique, UCAD, Dakar-Fann, Sénégal

Cite this paper:
Deng Xiaoyu, M. Diop and J.F. Diouris. Study of the Power Consumption of a Digital-Front-End Using Random Sampling. International Transaction of Electrical and Computer Engineers System. 2014; 2(2):73-80. doi: 10.12691/iteces-2-2-5

Abstract

Recently, irregular sampling techniques have been proposed for the design of digital front-end of a radio receiver. This front-end consist in the interface between the analog front-end and the baseband processing. The advantage of these techniques is the simplification of the sampling frequency conversion and the channel selection. The objective of the proposed work is to study if a gain in power consumption is also obtained. In this paper, the major research is the digital-front-end power consumption by using random sampling. Firstly, we introduce the methods of random sampling JRS (Jitter random sampling) and ARS (Additive random sampling). Then we use these methods to generate the random clock, select the hardware as mixed platform with ADC and FPGA and implement different solutions. At last, we measure the power consumption of different solutions and make a comparison.

Keywords:
JRS ARS FPGA ADC power consumption

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