Design of an Efficient Dedicated Low Power High Speed Full Adder

Asirbad Behera¹, Manas Ranjan Jena^1, , Abhinna Das¹ and Narendra Kumar Pattnayak¹

¹Deparment of ETC, SIET, DHENKANAL, ODISHA, INDIA

Cite this paper:
Asirbad Behera, Manas Ranjan Jena, Abhinna Das and Narendra Kumar Pattnayak. Design of an Efficient Dedicated Low Power High Speed Full Adder. Journal of Embedded Systems. 2014; 2(3):35-38. doi: 10.12691/jes-2-3-1

Abstract

In this paper, we have designed an efficient full adder with high speed & low power. As day by day more complex arithmetic circuits are presented, the power consumption becomes more important. Increasing demand for fast growing technologies in mobile electronic devices such as cellular phones, PDA’s and laptop computers requires the use of a low-power Full Adder in VLSI system. One way to reduce the power by reducing the power. However, decreasing power supply increases the circuit’s delay which is in contrast with high speed. So the power delay product (PDP) represents a trade-off between two compromising feature of power dissipitation and circuit delay. The new high speed high performance full adder is implemented by using CMOS technology. Simulation has been carried out on “MENTOGRAPHICS TOOLS” on 250 nm technology. Modification was done to optimize W/L ratio with different power supply. Results were compared with previously done single bit full adder circuit in terms of power, delay and power delay product (PDP).The results involves better performance compared to traditional adders.

Keywords:
PDA CMOS VLSI PDP NMOS

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