A Novel Dedicated Low Power 64 Bit Digital Comparator Using Cmos Logic

Shilparani Panda¹, Asirbad Behera¹, Manas Ranjan Jena^2, and Snigdharani Nath¹

¹Deparment of ETC, SIET, DHENKANAL,ODISHA

²Deparment of ELTCE, VSSUT, BURLA, ODISHA

Cite this paper:
Shilparani Panda, Asirbad Behera, Manas Ranjan Jena and Snigdharani Nath. A Novel Dedicated Low Power 64 Bit Digital Comparator Using Cmos Logic. Journal of Embedded Systems. 2014; 2(2):28-31. doi: 10.12691/jes-2-2-2

Abstract

In this paper we have designed a novel dedicated low power 64 bit digital comparator. Magnitude comparison is one of the basic functions used for sorting in microprocessor, digital signal processing, so a high performance, effective magnitude comparator is required. The main objective of this paper is to provide new low power, area solution for Very Large Scale Integration (VLSI) designers. A Low Power 64-bit CMOS binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on power delay product. Modifications are done in existing 64-bit binary comparator design to improve the PDP of the circuit. Simulation of the proposed design is performed at 180 nm technology in Tanner EDA Tool.

Keywords:
Binary comparator digital arithmetic Power delay product (pdp) CMOS logic

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