A Novel System-on-Chip (SoC) Integration Open Core Protocol (OCP) Bus with Multiple Master & Slave Support

Snigdharani Nath¹, Manas Ranjan Jena^2, and Shilparani Panda¹

¹Deparment of ETC, SIET, DHENKANAL,ODISHA

²Deparment of ELTCE, VSSUT, BURLA, ODISHA

Cite this paper:
Snigdharani Nath, Manas Ranjan Jena and Shilparani Panda. A Novel System-on-Chip (SoC) Integration Open Core Protocol (OCP) Bus with Multiple Master & Slave Support. Journal of Embedded Systems. 2014; 2(2):23-27. doi: 10.12691/jes-2-2-1

Abstract

In this paper, we have designed a System-on-Chip (SoC) Integration with Open Core Protocol (OCP) both master and slave cores particularly in the burst and in the tag mode. The master core is responsible for initiating the communication on the bus. The slave core is the device that has been addressed by the master in order to establish the communication. Multiple OCP transfers can be linked into a burst transaction Cores such as DRAM controllers can supply the second related piece of data much faster than the first Bursts allow a target to know that there are more transfers coming, so it can pre-fetch. Tags allow out-of-order return of responses and out-of-order commit of write data. In IP core plug-and-play reuse, cores need to be coupled from one another using a clearly specified core interface protocol. The core must be portable from one SOC design to the next without integration rework. Taking advantage of the increasing density of IC process technologies remains extremely dependant on a formidable challenge. Adapting cores from chip design to chip design to make them fit with the rest of the system-on-a-chip (SOC) has become for a while a totally inefficient and unproductive methodology. Each time a core is to be integrated into a new system the system integrator is hampered by massive rework that reduces productivity.

Keywords:
System-on-Chip (SoC) interface IPs Open Core Protocol (OCP) FIFO

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