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Review of Leakage Power Reduction in CMOS Circuits

by Khushboo Kumari, Arun Agarwal, Jayvrat and Kabita Agarwal

American Journal of Electrical and Electronic Engineering. 2014, 2(4), 133-136. DOI: 10.12691/ajeee-2-4-2
Pub. Date: September 05, 2014Views: 31628 Downloads: 26405Like: 42Citations: 5

CMOS Leakage power VLSI circuits multimedia applications Static power Nano Scale LSSR

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