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N. Hanchate and N. Ranganathan,” Lector: A technique for leakage reduction in CMOS circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol. 12, no. 2, pp. 196-205, February 2004.

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Article

Review of Leakage Power Reduction in CMOS Circuits

1B.Tech Student, Department of Electronics & Communication Engineering, Institute of Technical Education and Research, Siksha ‘O’ Anusandhan University, Khandagiri Square, Bhubaneswar, India

2Department of Electronics & Communication Engineering, Institute of Technical Education and Research, Siksha ‘O’ Anusandhan University, Khandagiri Square, Bhubaneswar, India

3Department Electronics & Telecommunication Engineering, CV Raman College of Engineering, Bhubaneswar, India


American Journal of Electrical and Electronic Engineering. 2014, Vol. 2 No. 4, 133-136
DOI: 10.12691/ajeee-2-4-2
Copyright © 2014 Science and Education Publishing

Cite this paper:
Khushboo Kumari, Arun Agarwal, Jayvrat, Kabita Agarwal. Review of Leakage Power Reduction in CMOS Circuits. American Journal of Electrical and Electronic Engineering. 2014; 2(4):133-136. doi: 10.12691/ajeee-2-4-2.

Correspondence to: Arun  Agarwal, Department of Electronics & Communication Engineering, Institute of Technical Education and Research, Siksha ‘O’ Anusandhan University, Khandagiri Square, Bhubaneswar, India. Email: arunagrawal@soauniversity.ac.in

Abstract

Recent Technological advances in Wireless Communication has shown the convergence of terminals and networks that support multimedia and real-time applications. This obviously puts an immense pressure on battery of any mobile device. The CMOS has been the leading technology in today’s world of mobile communication due to its low power consumption. Reduction of leakage power in CMOS has been the research interest for the last couple of years. In CMOS integrated circuit design there is an important trade-off between technology scaling and static power consumption. In today’s CMOS technology the leakage power consumption plays a significant role. As we approaching to nano-scale design the total chip power consumption becomes dependent on leakage power. Increasing the battery life in mobile wireless communication and mobile computing and similar other applications is the topic of research now-a days... Further, since the leakage of battery exists even when devices are in idle state makes leakage power loss most critical in CMOS VLSI circuits. Many techniques have been evolved to tackle the problem and its still in progress. This paper mainly focuses on the review of various works done in this field till today’s date. Further a review of recent work done on a new technique LSSR (Lector Stack State Retention Technique) is discussed in the paper.

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