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A. Bayrakci and A. Akkas, “Reduced delay BCD adder”, Proc.. IEEE 18th Int. Conf. on Application-specific Systems, Architectures and Processors, (ASAP), pp. 266-271, July 2007.

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Article

An Approach for Fast BCD Addition

1Department of Electrical Engineering, Texas A&M University-Texarkana, Texarkana, USA


American Journal of Electrical and Electronic Engineering. 2015, Vol. 3 No. 1, 13-16
DOI: 10.12691/ajeee-3-1-3
Copyright © 2015 Science and Education Publishing

Cite this paper:
Parag K. Lala. An Approach for Fast BCD Addition. American Journal of Electrical and Electronic Engineering. 2015; 3(1):13-16. doi: 10.12691/ajeee-3-1-3.

Correspondence to: Parag  K. Lala, Department of Electrical Engineering, Texas A&M University-Texarkana, Texarkana, USA. Email: plala@tamut.edu

Abstract

This paper presents a technique for fast addition of multi-digit BCD numbers. The addition of all columns can be performed simultaneously, and the carry values are utilized only in the final stage of the addition. Thus the traditional carry propagation process is drastically reduced, hence speeding up the addition process. The addition technique is used in the summation of partial products generated during a new multiplication approach proposed in the paper resulting in a faster multiplication.

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