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<!DOCTYPE ArticleSet PUBLIC "-//NLM//DTD PubMed 2.0//EN" "http://www.ncbi.nlm.nih.gov:80/entrez/query/static/PubMed.dtd">
<ArticleSet>
<Article>
<Journal>
<PublisherName>Science and Education Publishing</PublisherName>
<JournalTitle>Journal of Optoelectronics Engineering</JournalTitle>
<Issn>2372-4781</Issn>
<Volume>3</Volume>
<Issue>1</Issue>
<PubDate PubStatus="epublish">
<Year>2015</Year>
<Month>12</Month>
<Day>18</Day>
</PubDate>
</Journal>
<ArticleTitle>Etching Techniques for Thinning Silicon Wafer for Ultra Thin High Efficiency Interdigitated Back Contact Solar Cells</ArticleTitle>
<FirstPage>7</FirstPage>
<LastPage>14</LastPage>
<Language>EN</Language>
<AuthorList>
<Author>
<FirstName>Iduabo John</FirstName>
<LastName>Afa</LastName>
<Affiliation>Grup de Recerca en Micro i Nanotecnologies (MNT), Universitat Politècnica de Catalunya (UPC), C. Jordi Girona, Barcelona, Spain</Affiliation>
</Author>
<Author>
<FirstName>Gema</FirstName>
<LastName>López</LastName>
</Author>
<Author>
<FirstName>Pablo Rafael Ortega</FirstName>
<LastName>Villasclaras</LastName>
</Author>

</AuthorList>
<ArticleIdList>
<ArticleId IdType="pii">JOE2015312</ArticleId>
<ArticleId IdType="doi">10.12691/joe-3-1-2</ArticleId>
</ArticleIdList>
<History>
<PubDate PubStatus="received">
<Year>2015</Year>
<Month>8</Month>
<Day>30</Day>
</PubDate>
<PubDate PubStatus="revised">
<Year>2015</Year>
<Month>11</Month>
<Day>5</Day>
</PubDate>
<PubDate PubStatus="accepted">
<Year>2015</Year>
<Month>12</Month>
<Day>16</Day>
</PubDate>
</History>
<Abstract>High efficiency Interdigitated back contact (IBC) solar cells help reduce the area of solar panels needed to supply sufficient amount of energy for household consumption. We believe that a properly passivated IBC cell with the aid of light trapping schemes can maintain an efficiency of 20% even with thickness under 20 μm. In this work, photolithography and etching techniques are used for deep etching of crystalline Silicon (c-Si) wafer to a thickness less than 20 ̦m. Tetramethylammoniumhydroxide (TMAH) wet anisotropic etching and plasma based Reactive ion etching (RIE) are used with SPR 220-7.0 and SU-8 photoresists. SiO2 is used as making layer for TMAH etching. TMAH etch of a 4-inch c-Si wafer is done at a temperature of 80&#176;C for 8 hours. RIE of a quarter of a 4-inch c-Si wafer is done for 3 hours using SF6 as reactive gas. A baseline photolithography process flow for SU-8 photoresist deposition was developed. The etch rates of TMAH etch techniques fall within the range of 0.3 ̨C 0.45 μm/min and etch rates for RIE fall within the range of 1.2 ̨C 1.8 μm/min. The RIE shows capability of achieving smaller thickness sizes with greater advantages than the TMAH etching technique.</Abstract>
</Article>
</ArticleSet>
