@article{iteces2014253,
author={{Muduli, Giridhari and Pradhan, Bibhudatt and Jena, Manas Ranjan and Nath, Snigdharani},
title={Design of an Efficient Low Power 4-bit Arithmatic Logic Unit (ALU) Using VHDL},
journal={International Transaction of Electrical and Computer Engineers System},
volume={2},
number={5},
pages={144--148},
year={2014},
url={http://pubs.sciepub.com/iteces/2/5/3},
abstract={In this paper, we have designed an efficient low power 4-bit ALU using VHDL. Advancement in VLSI technology has allowed following Moore¡¯s law for doubling component density on a silicon chip after every three years. Though MOS transistors have been scaled down, increased interconnections have limited circuit density on a chip. Furthermore, the size of transistor is limited by hot-carrier phenomena and increase in electric field that lead to degradation of device performance and device lifetime. It has become essential to look into other methods of adding more functionality to a MOS transistor, such as, the multiple- input floating gate MOS transistor structure proposed by Shibata and Ohmi. An enhancement in the basic function of a transistor has, thus, allowed for designs to be implemented using fewer transistors and reduced interconnections. In published literature, many integrated circuits have been reported which are using multi-input floating gate MOSFETs in standard CMOS process. Thus using the advanced VLSI technology the proposed ALU design is more efficient.},
doi={10.12691/iteces-2-5-3}
publisher={Science and Education Publishing}
}