eng Science and Education Publishing American Journal of Electrical and Electronic Engineering 2328-7357 2020-09-10 8 4 120 124 10.12691/ajeee-8-4-4 AJEEE2020844 article Soumya Mourya 1 Raj Senani senani@ieee.org 1 Department of Electronics and Communication Engineering, Netaji Subhash University of Technology (formerly, NSIT), Sector 3, Dwarka, New-Delhi 110078, India In this communication, a new CMOS circuit configuration is proposed to realize a voltage-controlled negative resistance (VCNR) which has been implemented using only eight MOS transistors- all working in the saturation region. The value of the realized negative resistance is controlled by two identical and opposite external DC voltages. The workability of the proposed circuit has been confirmed by Cadence Virtuoso simulations and some sample results have been given. The proposed VCNR circuit has been shown to exhibit good linearity, has good variable negative resistance range from -1.05k? and -300? and offers a good operational frequency range up to around 100 MHz with total power dissipation between 0.5mW- 8.73mW only. http://pubs.sciepub.com/ajeee/8/4/4/ajeee-8-4-4.pdf JFET MOSFET CMOS voltage-controlledresistance voltage-controlled negative resistance