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Article

Studying the Impact of Scheduler Implementation on Task Jitter in Real-Time Resource-Constrained Embedded Systems

1Department of Electrical Engineering, College of Engineering and Islamic Architecture, Umm Al-Qura University, Makkah, KSA


Journal of Embedded Systems. 2014, 2(3), 39-52
DOI: 10.12691/jes-2-3-2
Copyright © 2014 Science and Education Publishing

Cite this paper:
Mouaaz Nahas. Studying the Impact of Scheduler Implementation on Task Jitter in Real-Time Resource-Constrained Embedded Systems. Journal of Embedded Systems. 2014; 2(3):39-52. doi: 10.12691/jes-2-3-2.

Correspondence to: Mouaaz  Nahas, Department of Electrical Engineering, College of Engineering and Islamic Architecture, Umm Al-Qura University, Makkah, KSA. Email: mmnahas@uqu.edu.sa

Abstract

Over recent decades, many studies have considered the development, assessment and refinement of scheduling algorithms for use in real-time embedded applications. Various studies have also considered the impact of variations in the interval between the executions of periodic tasks (i.e. jitter) on the behaviour of such systems. Despite interest in both of these areas, there has been comparatively little attention paid to the impact of scheduler implementation techniques on jitter behaviour. This is unfortunate because – as we demonstrate in the course of this paper – there is a ‘one-to-many’ mapping between scheduler algorithms and scheduler implementations, and even comparatively small changes in the scheduler implementation can have a significant impact on jitter behaviour. Throughout this paper, our focus is on implementations of a form of “cyclic executive” which is one of the simplest scheduling algorithms in widespread use. The results presented demonstrate that – even for this very simple scheduling algorithm – implementation decisions can have a significant impact on both jitter behaviour and on resource requirements. We would expect that the results obtained would also apply to more complicated algorithms: indeed, as the algorithms grow more complicated, we would expect that the number of implementation options would increase, with a corresponding increase in the jitter variation.

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References

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Article

Design of an Efficient Dedicated Low Power High Speed Full Adder

1Deparment of ETC, SIET, DHENKANAL, ODISHA, INDIA


Journal of Embedded Systems. 2014, 2(3), 35-38
DOI: 10.12691/jes-2-3-1
Copyright © 2014 Science and Education Publishing

Cite this paper:
Asirbad Behera, Manas Ranjan Jena, Abhinna Das, Narendra Kumar Pattnayak. Design of an Efficient Dedicated Low Power High Speed Full Adder. Journal of Embedded Systems. 2014; 2(3):35-38. doi: 10.12691/jes-2-3-1.

Correspondence to: Manas  Ranjan Jena, Deparment of ETC, SIET, DHENKANAL, ODISHA, INDIA. Email: manas.synergy@gmail.com

Abstract

In this paper, we have designed an efficient full adder with high speed & low power. As day by day more complex arithmetic circuits are presented, the power consumption becomes more important. Increasing demand for fast growing technologies in mobile electronic devices such as cellular phones, PDA’s and laptop computers requires the use of a low-power Full Adder in VLSI system. One way to reduce the power by reducing the power. However, decreasing power supply increases the circuit’s delay which is in contrast with high speed. So the power delay product (PDP) represents a trade-off between two compromising feature of power dissipitation and circuit delay. The new high speed high performance full adder is implemented by using CMOS technology. Simulation has been carried out on “MENTOGRAPHICS TOOLS” on 250 nm technology. Modification was done to optimize W/L ratio with different power supply. Results were compared with previously done single bit full adder circuit in terms of power, delay and power delay product (PDP).The results involves better performance compared to traditional adders.

Keywords

References

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Article

A Low Cost High Precision Virtual Instrumentation for Potentiometric Titration

1Department of Electronics, J. B. Science College, Wardha, India

2Department of Electronics, Nagpur university Campus, Nagpur, India


Journal of Embedded Systems. 2014, 2(2), 32-34
DOI: 10.12691/jes-2-2-3
Copyright © 2014 Science and Education Publishing

Cite this paper:
V. M. Ghodki, S. J. Sharma, S. Rajagopalan. A Low Cost High Precision Virtual Instrumentation for Potentiometric Titration. Journal of Embedded Systems. 2014; 2(2):32-34. doi: 10.12691/jes-2-2-3.

Correspondence to: V.  M. Ghodki, Department of Electronics, J. B. Science College, Wardha, India. Email: vilasghodki@rediffmail.com

Abstract

We propose a high precision personal computer (PC) based virtual instrumentation for potentiometric titration technique using Advantech USB 4711A data acquisition module. The entire titration including online data acquisition followed by immediate online analysis of data to get information about concentration of unknown sample is completed within a couple of seconds. The test setup is developed in our laboratory using Advantech’s data acquisition card, USB 4711A interfaced to the IBM compatible PC, operated under windows 7 operating system. A simple and inexpensive signal processing circuit is designed in our laboratory using off-the-shelf components, to amplify signal received from glass electrode. Powerful and effective data acquisition software VB.NET is used at back end as well as front end to accomplish data acquisition, parameter setting, file manipulation, control and synchronization of the other functions involved in the measurements. The control panel directly displays the strength of liquid under test at a given temperature.

Keywords

References

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[[5]  Ghodki V. M., “Development of PC based Technique for Acoustic Measurements”, Ph. D. Thesis, RTM Nagpur University, March 2005.
 
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Article

A Novel Dedicated Low Power 64 Bit Digital Comparator Using Cmos Logic

1Deparment of ETC, SIET, DHENKANAL,ODISHA

2Deparment of ELTCE, VSSUT, BURLA, ODISHA


Journal of Embedded Systems. 2014, 2(2), 28-31
DOI: 10.12691/jes-2-2-2
Copyright © 2014 Science and Education Publishing

Cite this paper:
Shilparani Panda, Asirbad Behera, Manas Ranjan Jena, Snigdharani Nath. A Novel Dedicated Low Power 64 Bit Digital Comparator Using Cmos Logic. Journal of Embedded Systems. 2014; 2(2):28-31. doi: 10.12691/jes-2-2-2.

Correspondence to: Manas  Ranjan Jena, Deparment of ELTCE, VSSUT, BURLA, ODISHA. Email: manas.synergy@gmail.com

Abstract

In this paper we have designed a novel dedicated low power 64 bit digital comparator. Magnitude comparison is one of the basic functions used for sorting in microprocessor, digital signal processing, so a high performance, effective magnitude comparator is required. The main objective of this paper is to provide new low power, area solution for Very Large Scale Integration (VLSI) designers. A Low Power 64-bit CMOS binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on power delay product. Modifications are done in existing 64-bit binary comparator design to improve the PDP of the circuit. Simulation of the proposed design is performed at 180 nm technology in Tanner EDA Tool.

Keywords

References

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Article

A Novel System-on-Chip (SoC) Integration Open Core Protocol (OCP) Bus with Multiple Master & Slave Support

1Deparment of ETC, SIET, DHENKANAL,ODISHA

2Deparment of ELTCE, VSSUT, BURLA, ODISHA


Journal of Embedded Systems. 2014, 2(2), 23-27
DOI: 10.12691/jes-2-2-1
Copyright © 2014 Science and Education Publishing

Cite this paper:
Snigdharani Nath, Manas Ranjan Jena, Shilparani Panda. A Novel System-on-Chip (SoC) Integration Open Core Protocol (OCP) Bus with Multiple Master & Slave Support. Journal of Embedded Systems. 2014; 2(2):23-27. doi: 10.12691/jes-2-2-1.

Correspondence to: Manas  Ranjan Jena, Deparment of ELTCE, VSSUT, BURLA, ODISHA. Email: manas.synergy@gmail.com

Abstract

In this paper, we have designed a System-on-Chip (SoC) Integration with Open Core Protocol (OCP) both master and slave cores particularly in the burst and in the tag mode. The master core is responsible for initiating the communication on the bus. The slave core is the device that has been addressed by the master in order to establish the communication. Multiple OCP transfers can be linked into a burst transaction Cores such as DRAM controllers can supply the second related piece of data much faster than the first Bursts allow a target to know that there are more transfers coming, so it can pre-fetch. Tags allow out-of-order return of responses and out-of-order commit of write data. In IP core plug-and-play reuse, cores need to be coupled from one another using a clearly specified core interface protocol. The core must be portable from one SOC design to the next without integration rework. Taking advantage of the increasing density of IC process technologies remains extremely dependant on a formidable challenge. Adapting cores from chip design to chip design to make them fit with the rest of the system-on-a-chip (SOC) has become for a while a totally inefficient and unproductive methodology. Each time a core is to be integrated into a new system the system integrator is hampered by massive rework that reduces productivity.

Keywords

References

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Article

Decision Based Median Filter Algorithm Using Resource Optimized FPGA to Extract Impulse Noise

1Research Scholar, Department of Technology, Shivaji University, Kolhapur

2Professor, Department of Technology, Shivaji University, Kolhapur


Journal of Embedded Systems. 2014, 2(1), 18-22
DOI: 10.12691/jes-2-1-4
Copyright © 2014 Science and Education Publishing

Cite this paper:
Rutuja N. Kulkarni, P.C. Bhaskar. Decision Based Median Filter Algorithm Using Resource Optimized FPGA to Extract Impulse Noise. Journal of Embedded Systems. 2014; 2(1):18-22. doi: 10.12691/jes-2-1-4.

Correspondence to: Rutuja  N. Kulkarni, Research Scholar, Department of Technology, Shivaji University, Kolhapur. Email: kulkarni.rutuja@gmail.com

Abstract

Median filter is a non-linear filter used in image processing for impulse noise removal. It finds its typical application in the situations where edges are to be preserved for higher level operations like segmentation, object recognition etc. This paper presents accurate and efficient noise detection and filtering algorithm for impulse noise removal. The algorithm includes two stages: noise detection followed by noise filtering. The proposed algorithm replaces the noisy pixel by clipping median value when other pixel values, 0’ s or 255’ s are present in the selected window and when all the pixel values are 0’ s and 255’ s then the noise pixel is replaced by mean value of all the elements present in the selected window. This median filter was designed, simulated and synthesized on the Xilinx family of FPGAs (XC3S500E of Spartan-3E). The VHDL was used to design the above 2-D median filter using ISE (Xilinx) tool & tested & compared for different grayscale images.

Keywords

References

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[7]  S. Marshall, “New direct design method for weighted order statistic filters,” VISP, vol. 151, no. 1, pp. 1-8, February 2004.
 
[8]  M. C Hanumantharaju, M. Ravishankar, D. R Rameshbabu and S. B Satish “An Efficient VLSI Architecture for Adaptive Rank Order Filter for Image Noise Removal” International Journal of Information and Electronics Engineering, Vol. 1, No. 1, July 2011.
 
[9]  Tarek M. Bittibssi, Gouda I. Salama, Yehia Z. Mehaseb and Adel E. Henawy “Image Enhancement Algorithms using FPGA” International Journal of Computer Science & Communication Networks, Vol. 2 (4), 536-542.
 
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Article

Design of Embedded Sing-around System for Ultrasonic Velocity Measurements in Liquids

1Department of Electronics, RTM Nagpur University, Nagpur, India

2Department of Electronics, Anand Niketan College, Warora, India

3Department of Electronics, J. B. Science College, Wardha, India


Journal of Embedded Systems. 2014, 2(1), 15-17
DOI: 10.12691/jes-2-1-3
Copyright © 2014 Science and Education Publishing

Cite this paper:
S. J. Sharma, A. C. Balharpure, A. S. Pande, S. U. Dubey, G. K. Singh, V. M. Ghodki, S. Rajagopalan. Design of Embedded Sing-around System for Ultrasonic Velocity Measurements in Liquids. Journal of Embedded Systems. 2014; 2(1):15-17. doi: 10.12691/jes-2-1-3.

Correspondence to: S.  J. Sharma, Department of Electronics, RTM Nagpur University, Nagpur, India. Email: sharmasat@gmail.com

Abstract

Among the pulse techniques in ultrasonics, sing around technique is widely used for measurements of ultrasonic velocity in liquids and solids. It is simple, versatile and highly accurate for absolute and relative ultrasonic velocity measurements. In the present work, an embedded sing around system, at operating frequency of 2 MHz, is designed around PIC 18F4550 microcontroller. Pulser and receiver circuits have been designed using locally available electronic components. Necessary controls have been dumped or embedded as software in the microcontroller to add intelligence to the sing around system. The designed system is compact, stand-alone, reliable, accurate and portable with onboard display of the ultrasonic velocity of propagation in the sample under study. Ultrasonic velocity measurements have been carried out in standard liquids and found to be in well agreement with the values reported in the literature.

Keywords

References

[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[
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[12]  Yogurtcu Y. K., Lambson E. F., Miller A. J. and Saunders G.A., “An Apparatus for High Precision Measurements of Ultrasonic Wave Velocity”, Ultrason., 155-159 (1981).
 
[13]  Soitkar V. S., Sunnapwar K. P. and Navaneeth G. N., “A Solid State Pulsed Sing-Around System for Ultrasonic Velocity Measurements”, J. of Pure & Appl. Phys., 19, 555-559 (1981).
 
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[23]  Ghodki V. M., “Development of PC based Technique for Acoustic Measurements”, Ph. D. Thesis, RTM Nagpur University, March 2005.
 
[24]  Dubey P. K., “Design and Study of Instrumentation for Ultrasonic Characterisation of Polymers”, Ph. D. Thesis, RTM Nagpur University, October 2006.
 
[25]  Pendsey V. M., “Development of PC based Pulse Technique for Ultrasonic Measurements”, Ph. D. Thesis, RTM Nagpur University, October 2011.
 
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[27]  Rajagopalan S., Sharma S. J. and Ghodki V. M., “PC based Design of Single Pulse Sender/receiver Technique for Ultrasonic Velocity Measurements”, J. Pure & Appl. Ultason. 29, 143-145 (2007).
 
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Article

System on Chip (PSoC) Control for High Current Magnet Power Supply

1Department of Electronics & Instrumentation, Bharathiar University, Coimbatore


Journal of Embedded Systems. 2014, 2(1), 11-14
DOI: 10.12691/jes-2-1-2
Copyright © 2014 Science and Education Publishing

Cite this paper:
K.G. Padmasine, S. Muruganand. System on Chip (PSoC) Control for High Current Magnet Power Supply. Journal of Embedded Systems. 2014; 2(1):11-14. doi: 10.12691/jes-2-1-2.

Correspondence to: K.G.  Padmasine, Department of Electronics & Instrumentation, Bharathiar University, Coimbatore. Email: padmasinechandra@gmail.com

Abstract

This paper describes a high current magnet power supply control through a Programmable System on Chip (PSoC) based embedded design and its menu driven control program written in Virtual instrument program. This design supports a wider dynamic range of current from 0 to 120 amperes in steps of 0.1 amps to the magnet power supply. It also has the fine tuning facility of current in the range of 0.01 amps to the magnet. In the existing BRUKER make B-CN-120 model power supply a programmable port has been implemented through which the PSoC embedded design interact via PCs USB port configured through Lab VIEW program resides in the PC. The successful PSoC design implementation simplifies the automation of BRUKER Magnet power supply.

Keywords

References

[[[[[[[[[[
[[1]  BRUKER Magnet power supply datasheet. http://www.bruker.com.
 
[[2]  Anshu Kandhari and Naman Jain, Seven steps to embedded designs made easier with PSoC Creator. Cypress Semiconductor-March 14, 2012.
 
[[3]  J. Jayapandian. Data Acquisition and Control System-the PSoC way, AN 2335, Cypress Micro Systems, 21st July 2006, p. 1-7.
 
[[4]  Cypress semiconductor.
 
[[5]  National instrumentation.
 
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[6]  S. Sharonov and J. M. Nogiec, AN EMBEDDED POWER SUPPLY CONTROLLER, 0-7803-4376-X/98/$10.00 1998 IEEE.
 
[7]  C. Y. Wu ET AL., Control Of The Pulse Magnet Power Supply By Epics IOC Embedded PLC, Proceedings of IPAC’10, Kyoto, Japan WEPEB020.
 
[8]  Uchiyama et. al., “Development of Embedded EPICS on F3RP61-2L”, PCaPAC08, Ljubljana, Slovenia, October 20-23, 2008, p. 145.
 
[9]  M. Komiyama et. al., “Upgrading the Control System of RIKEN RI Beam Factory for New. Injector”, Proceeding of the ICALEPCS 2009, Kobe, Japan, October 12-16, 2009, TPPB11.
 
[10]  J. Odagiri, et al., “Development of Embedded EPICS on F3RP61-2L”, Proceedings of the 5th Annual Meeting of Particle Accelerator Society of Japan and the 33rd Linear Accelerator Meeting in Japan, Hiroshima, August 6-9, 2008, FO27.
 
[11]  J. Odagiri, et al., “Application of EPICS on F3RP61 to Accelerator Control”, Proceeding of the ICALEPCS 2009, Kobe, Japan, October 12-16, 2009, THD005.
 
[12]  J. Weber et al., Als Mini Ioc: An FPGA Embedded Processor Based Control System Module For Booster Magnet Ramping At The Als, Proceedings of PAC07, Albuquerque, New Mexico, USA FRPMS030.
 
[13]  K. Mikawa et al., Embedded Epics Controller For Kekb Pulsed Quadrupole Magnet Power Supply, Proceedings of ICALEPCS2009, Kobe, Japan.
 
[14]  S. Motohashi et al., “Data Acquisition System of Beam Loss Monitors of J-PARC Main Ring”, in this conference.
 
[15]  M. Nogiec, E. Desavouret, J. Pachnik, S. Sharonov, J. Sim, An Open Distributed Monitoring and Control System’, J. Proceedings of CHEP'97, April 1997, Berlin.
 
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Article

Estimating Message Latencies in Time-Triggered Shared-Clock Scheduling Protocols Built on CAN Network

1Department of Electrical Engineering, College of Engineering and Islamic Architecture, Umm Al-Qura University, Makkah, KSA


Journal of Embedded Systems. 2014, 2(1), 1-10
DOI: 10.12691/jes-2-1-1
Copyright © 2014 Science and Education Publishing

Cite this paper:
Mouaaz Nahas. Estimating Message Latencies in Time-Triggered Shared-Clock Scheduling Protocols Built on CAN Network. Journal of Embedded Systems. 2014; 2(1):1-10. doi: 10.12691/jes-2-1-1.

Correspondence to: Mouaaz  Nahas, Department of Electrical Engineering, College of Engineering and Islamic Architecture, Umm Al-Qura University, Makkah, KSA. Email: mmnahas@uqu.edu.sa

Abstract

The Controller Area Network (CAN) is an event-triggered protocol that is widely used in distributed real-time embedded systems. It has been demonstrated that a “Shared-Clock” (S-C) scheduling protocol can be used on top of CAN hardware to implement time-triggered network operations. Previous work in this area has led to the development of five different time-triggered S-C scheduling protocols referred to as: TTC-SCC1, TTC-SCC2, TTC-SCC3, TTC-SCC4 and TTC-SCC5 schedulers. This paper develops mathematical models for assessing message latencies between all communicating nodes in the different S-C scheduling protocols. In particular, the paper provides mathematical equations for estimating Master-to-Slave, Slave-to-Master, and Slave-to-Slave message latencies in all five schedulers. The paper then presents a small case study to allow a practical comparison of the communication behavior in the various S-C schedulers considered. The results show that the communication behavior, especially Slave-to-Slave message delays, can be improved significantly when TTC-SCC3, TTC-SCC4 and TTC-SCC5 scheduler implementations are used. The results also show that even a small selection of S-C scheduler implementations demonstrates a wide range of different patterns of behavior. It is therefore suggested that selection of the most appropriate scheduler will largely depend on requirements of the application for which the scheduler is intended.

Keywords

References

[[[[[[[[[[[[[[[[[[[
[[1]  Pont, M, Patterns for Time-Triggered Embedded Systems: Building Reliable Applications with the 8501 Family of Microcontrollers, Addison Wesley, 2001.
 
[[2]  Pont, M, “An object-oriented approach to software development for embedded systems implemented using C,” Transactions of the Institute of Measurement and Control, 25 (3). 217-238. 2003.
 
[[3]  Pont, M. J., and Banner, M. P, “Designing embedded systems using patterns: A case study,” Journal of Systems and Software, 71 (3). 201-213. 2004.
 
[[4]  Kurian, S., and Pont, M. J, “The maintenance and evolution of resource-constrained embedded systems created using design patterns,” Journal of Systems and Software, 80 (1). 32-41. 2007.
 
[[5]  Wang, H., Pont, M. J., and Kurian, S, “Patterns which help to avoid conflicts over shared resources in time-triggered embedded systems which employ a pre-emptive scheduler,” SAE Transactions, 115 (7). 795-83. 2005.
 
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[6]  Nahas, M, “Employing Two “Sandwich Delay” Mechanisms to Enhance Predictability of Embedded Systems Which Use Time-Triggered Co-operative Architectures,” International Journal of Software Engineering and Applications, 4 (7). 417-425. 2011.
 
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[18]  Ayavoo, D, The development of reliable X-by-wire systems: assessing the effectiveness of a 'simulation first' approach, PhD Thesis, University of Leicester. 2006.
 
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Article

Advanced Fuzzy Logic Model for Volume Based Traffic Signal Control

1Assistant Professor in Electronics and Telecommunication, VSSUT, Burla, Sambalpur, Odisha,India

2Student in Electronics and Telecommunication, VSSUT, Burla Sambalpur, Odisha, India


Journal of Embedded Systems. 2013, 1(1), 1-6
DOI: 10.12691/jes-1-1-1
Copyright © 2013 Science and Education Publishing

Cite this paper:
Bandan Kumar Bhoi, Abhipsa Panda, Sarthak Acharya. Advanced Fuzzy Logic Model for Volume Based Traffic Signal Control. Journal of Embedded Systems. 2013; 1(1):1-6. doi: 10.12691/jes-1-1-1.

Correspondence to: Bandan  Kumar Bhoi, Assistant Professor in Electronics and Telecommunication, VSSUT, Burla, Sambalpur, Odisha,India. Email: bandanuce@gmail.com

Abstract

This paper describes a functional Fuzzy Traffic Controller (FTC), which utilizes fuzzy logic algorithm to achieve a smart and flexible knowledge based system in hardware design while achieving better efficiency in the traffic control and minimizing traffic jam occurrences at interchange on road area. The designing part of FTC chip into verilog program eliminates the short comings of other custom facilities and conventional controller design available today. The Finite State Machine (FSM) of the FTC is coded in verilog for controlling the specific traffic flow application. The main features of FTC chip consist of various operational modes, safety features and capability through fuzzy logic algorithm.

Keywords

References

[[[[
[[1]  IEEE journal numbered 1-4244-0549-1, titled “Design and Implementation of an Intelligent Fuzzy VLSI Chip for Traffic Control Application” of 2006.
 
[[2]  Pitu Mirchandani, Larry Head. “RHODES Traffic Adaptive Control System,” Workshop on Adaptive Traffic Signal Control System, ATLAS Research Center, System and Industrial Engineering Department, The University of Arizona, 2001.
 
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[[4]  Richard P. Zanardo. “Digital Traffic Signal Controller,” unpublished master’s thesis, Bradley University, Department of Electrical and Computing Engineering and Technology, 1999.
 
[[5]  Ralf Niemann. “Hardware/Software Co-Design for Data Flow Dominated Embedded System,” University of Dortmund, Department of Computer Science XII, Germany, 1998.
 
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[6]  Aleksandar Bobrek and Justin Britten. “FPGA Traffic Light Controller,” unpublished master’s thesis, Electrical & Computer Engineering, University of Tennessee, 2001.
 
[7]  Cheng, P.J Denning. “One-Lane Traffic Controller,” unpublished master’s thesis, George Mason University, 2001.
 
[8]  Caig Roberts, “Traffic Controller – Intersection Simulator Board,” unpublished master’s thesis, The Arizona Laboratory for Applied Transport Research, Northern Arizona University, 1998.
 
[9]  James Fernstrom, Thomas Wenisch. “Traffic Controller Design in PLA,” unpublished master’s thesis, University of Rhode Island, Kingston, 1998.
 
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