Journal of Embedded Systems

ISSN (Print): 2376-7987

ISSN (Online): 2376-7979

Website: http://www.sciepub.com/journal/JES

Article

System on Chip (PSoC) Control for High Current Magnet Power Supply

1Department of Electronics & Instrumentation, Bharathiar University, Coimbatore


Journal of Embedded Systems. 2014, 2(1), 11-14
DOI: 10.12691/jes-2-1-2
Copyright © 2014 Science and Education Publishing

Cite this paper:
K.G. Padmasine, S. Muruganand. System on Chip (PSoC) Control for High Current Magnet Power Supply. Journal of Embedded Systems. 2014; 2(1):11-14. doi: 10.12691/jes-2-1-2.

Correspondence to: K.G.  Padmasine, Department of Electronics & Instrumentation, Bharathiar University, Coimbatore. Email: padmasinechandra@gmail.com

Abstract

This paper describes a high current magnet power supply control through a Programmable System on Chip (PSoC) based embedded design and its menu driven control program written in Virtual instrument program. This design supports a wider dynamic range of current from 0 to 120 amperes in steps of 0.1 amps to the magnet power supply. It also has the fine tuning facility of current in the range of 0.01 amps to the magnet. In the existing BRUKER make B-CN-120 model power supply a programmable port has been implemented through which the PSoC embedded design interact via PCs USB port configured through Lab VIEW program resides in the PC. The successful PSoC design implementation simplifies the automation of BRUKER Magnet power supply.

Keywords

References

[1]  BRUKER Magnet power supply datasheet. http://www.bruker.com.
 
[2]  Anshu Kandhari and Naman Jain, Seven steps to embedded designs made easier with PSoC Creator. Cypress Semiconductor-March 14, 2012.
 
[3]  J. Jayapandian. Data Acquisition and Control System-the PSoC way, AN 2335, Cypress Micro Systems, 21st July 2006, p. 1-7.
 
[4]  Cypress semiconductor.
 
[5]  National instrumentation.
 
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[6]  S. Sharonov and J. M. Nogiec, AN EMBEDDED POWER SUPPLY CONTROLLER, 0-7803-4376-X/98/$10.00 1998 IEEE.
 
[7]  C. Y. Wu ET AL., Control Of The Pulse Magnet Power Supply By Epics IOC Embedded PLC, Proceedings of IPAC’10, Kyoto, Japan WEPEB020.
 
[8]  Uchiyama et. al., “Development of Embedded EPICS on F3RP61-2L”, PCaPAC08, Ljubljana, Slovenia, October 20-23, 2008, p. 145.
 
[9]  M. Komiyama et. al., “Upgrading the Control System of RIKEN RI Beam Factory for New. Injector”, Proceeding of the ICALEPCS 2009, Kobe, Japan, October 12-16, 2009, TPPB11.
 
[10]  J. Odagiri, et al., “Development of Embedded EPICS on F3RP61-2L”, Proceedings of the 5th Annual Meeting of Particle Accelerator Society of Japan and the 33rd Linear Accelerator Meeting in Japan, Hiroshima, August 6-9, 2008, FO27.
 
[11]  J. Odagiri, et al., “Application of EPICS on F3RP61 to Accelerator Control”, Proceeding of the ICALEPCS 2009, Kobe, Japan, October 12-16, 2009, THD005.
 
[12]  J. Weber et al., Als Mini Ioc: An FPGA Embedded Processor Based Control System Module For Booster Magnet Ramping At The Als, Proceedings of PAC07, Albuquerque, New Mexico, USA FRPMS030.
 
[13]  K. Mikawa et al., Embedded Epics Controller For Kekb Pulsed Quadrupole Magnet Power Supply, Proceedings of ICALEPCS2009, Kobe, Japan.
 
[14]  S. Motohashi et al., “Data Acquisition System of Beam Loss Monitors of J-PARC Main Ring”, in this conference.
 
[15]  M. Nogiec, E. Desavouret, J. Pachnik, S. Sharonov, J. Sim, An Open Distributed Monitoring and Control System’, J. Proceedings of CHEP'97, April 1997, Berlin.
 
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Article

Design of Embedded Sing-around System for Ultrasonic Velocity Measurements in Liquids

1Department of Electronics, RTM Nagpur University, Nagpur, India

2Department of Electronics, Anand Niketan College, Warora, India

3Department of Electronics, J. B. Science College, Wardha, India


Journal of Embedded Systems. 2014, 2(1), 15-17
DOI: 10.12691/jes-2-1-3
Copyright © 2014 Science and Education Publishing

Cite this paper:
S. J. Sharma, A. C. Balharpure, A. S. Pande, S. U. Dubey, G. K. Singh, V. M. Ghodki, S. Rajagopalan. Design of Embedded Sing-around System for Ultrasonic Velocity Measurements in Liquids. Journal of Embedded Systems. 2014; 2(1):15-17. doi: 10.12691/jes-2-1-3.

Correspondence to: S.  J. Sharma, Department of Electronics, RTM Nagpur University, Nagpur, India. Email: sharmasat@gmail.com

Abstract

Among the pulse techniques in ultrasonics, sing around technique is widely used for measurements of ultrasonic velocity in liquids and solids. It is simple, versatile and highly accurate for absolute and relative ultrasonic velocity measurements. In the present work, an embedded sing around system, at operating frequency of 2 MHz, is designed around PIC 18F4550 microcontroller. Pulser and receiver circuits have been designed using locally available electronic components. Necessary controls have been dumped or embedded as software in the microcontroller to add intelligence to the sing around system. The designed system is compact, stand-alone, reliable, accurate and portable with onboard display of the ultrasonic velocity of propagation in the sample under study. Ultrasonic velocity measurements have been carried out in standard liquids and found to be in well agreement with the values reported in the literature.

Keywords

References

[1]  Cedrone N. P, and Curran D. R., “Electronic Pulse Method for Measuring the Velocity of Sound in Liquids and Solids”, J. Acoust. Soc. Am. 26(6), 963-967 (1954).
 
[2]  Forgacs R. L., “Improvements in the Sing-Around Technique for Ultrasonic Velocity Measurements”, J. Acoust. Soc. Am. 32(12), 1697 (1960).
 
[3]  H. Asada., “Sing-around Type Ultrasonic Measurement Instrument”, United States Patent 3,710,621 (Jan. 16, 1973).
 
[4]  Herzfeld K. F., “Fifty Years of Physical Ultrasonics”, J. Acoust. Soc. Am., 39(5.1), 813-825 (1966).
 
[5]  Khimunin A. S., “Circuit Errors in Measurement of the Velocity of Sound in Liquids by means of a Sing-around Velocimeter”, Sov. Phy. Acoust., 14(1), 75-78 (1968).
 
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[6]  Kononenko V. S. and Yakovlev V. F., “Precision method for measuring the velocity of ultrasound in liquid at 0.7 - 30 MHz”, Sov. Phys. Acoust, 15(1), 65-68 (1969).
 
[7]  D’Arrigo G., Marietti P., and Taraglia P., “A new form of the Sing-Around Technique for Ultra-Sonic Velocity Measurements”, Letts. al Nuovo Cimento, 1(4), 105-114 (1970).
 
[8]  Lacy L. L. and Daniel A. C., “Measurements of Ultrasonic Velocities using a Digital Averaging Technique”, J. Acoust. Soc. Am.,52(1.2), 189-195 (1972).
 
[9]  Srinivasan K. R., Krishnan S., Shivaraman A., Nagarajan N., Ramakrishnan J. and Gopal E. S. R., “A Versatile Ultrasonic Pulse Echo Interferometer for Precise Velocity Measurement in Solids”, Symposium on Transducer Technology, Cochin (India), 283-288 (1975).
 
[10]  North M. A., Pethrick R. A. and Phillips W. D., “Ultrasonic studies of solid poly(alkyl methacrylates)”, Polym., 18, 324-326 (1977).
 
[11]  Sunnapwar K. P., Soitkar V. S., Dutt R. S. and Navaneeth G. N., “Automated Pulse Repetition Time Measurements in a Sing-around system in Ultrasonics”, Acoust. Letts, 4(6), 104-109 (1980).
 
[12]  Yogurtcu Y. K., Lambson E. F., Miller A. J. and Saunders G.A., “An Apparatus for High Precision Measurements of Ultrasonic Wave Velocity”, Ultrason., 155-159 (1981).
 
[13]  Soitkar V. S., Sunnapwar K. P. and Navaneeth G. N., “A Solid State Pulsed Sing-Around System for Ultrasonic Velocity Measurements”, J. of Pure & Appl. Phys., 19, 555-559 (1981).
 
[14]  Adachi K., Harrison G., Lamb J., North M. A., Pethrick A. R., “High Frequency Ultrasonic Studies of Polyethylene”, Polym., 22, 1032-1039 (1981).
 
[15]  Rajagopalan S., “Ultrasonic Velocity Measurement for High Accuracy”, CSIO Communication, 9(4), 131-136 (1982).
 
[16]  Woodward B. and Salman N. A., “A Programmable Ultrasonic Velocimeter”, Acoust. Letts, 6(8), 110-114 (1983).
 
[17]  Agnihotri P. K., Adgaonkar C. S. and Bedare C. Y., “A Low Cost Solid Pulsed System for Ultrasonic Velocity and Absorption Measurement”, Arch. of Acoust., 12(3-4), 301-310 (1987).
 
[18]  Adgaonkar C. S. and Agnihotri P. K., “A Low Cost Solid State Sender-receiver System for Ultrasonic Velocity Measurement”, Res. & Ind. 33, 139-143 (1988).
 
[19]  Tiwari S. A., Rajagopalan S. and Amirtha V., “A Frequency Selectable Sing-around System for Measurement of Ultrasonic Velocity”, Acoust. Letts, 14(7), 135-140 (1991).
 
[20]  Ernst S., Marczak W., Manikowski R., Zorebski E. and Zorebski M., “A Sing-around Apparatus for Group Velocity Measurement in Liquids. Testing by Standard Liquids and Discussion of the Errors”, Acoust. Letts, 15(7), 123-130 (1992).
 
[21]  Yawale S. P. and Pakade S. V., “Solid State Variable Frequency Pulser-receiver System for Ultrasonic Measurements”, J. of Pure & Appl. Phy., 33, 638-642 ( 1995).
 
[22]  Nakmura K., Okado T. and Ueha S.. “Measuring the Optical Length of a Plastic Optical Fibre using the Sing-around Method and its Sensor Applications”, J. Opt. A.: Pure & Appl. Opt. 3(5), L17-L19 (2001).
 
[23]  Ghodki V. M., “Development of PC based Technique for Acoustic Measurements”, Ph. D. Thesis, RTM Nagpur University, March 2005.
 
[24]  Dubey P. K., “Design and Study of Instrumentation for Ultrasonic Characterisation of Polymers”, Ph. D. Thesis, RTM Nagpur University, October 2006.
 
[25]  Pendsey V. M., “Development of PC based Pulse Technique for Ultrasonic Measurements”, Ph. D. Thesis, RTM Nagpur University, October 2011.
 
[26]  Kalyana Raman S. B., Arjav and Jayakumari T., “PC based Ultrasonic Instrumentation for Liquids”, J. Instrum. Soc. Ind. 37(2), 150-156 (2007).
 
[27]  Rajagopalan S., Sharma S. J. and Ghodki V. M., “PC based Design of Single Pulse Sender/receiver Technique for Ultrasonic Velocity Measurements”, J. Pure & Appl. Ultason. 29, 143-145 (2007).
 
[28]  Rajagopalan S., Sharma S. J. and Ghodki V. M., “Design of PC based Sing-around System”, J. Instrum. Soc. Ind. 37(4), 206-211 (2007).
 
[29]  Rajagopalan S., Sharma S. J. and Ghodki V. M., “Design of Virtual Sing-around System for Precise Ultrasonic Velocity Measurements”, Elect. J. Tech. Acoust. 5, (2010).
 
[30]  Singh G. K., Pendsey V. M., Sharma S. J. and Rajagopalan S., “Ultrasonic Velocity Measurements using GSM Network”, J. Instrum. Soc. Ind. 39(4), 258-259 (2009).
 
[31]  Singh G. K., Pendsey V. M., Sharma S. J. and Rajagopalan S., “Measurement of Ultrasonic Velocity in Liquids Using Wireless Technology: SMS”, ISOR J. Appl. Phys. 1(3), 20-22 (2012).
 
[32]  Singh G. K., Pendsey V. M., Sharma S. J. and Rajagopalan S., “Remote Monitoring of Pulser-receiver Setup for Ultrasonic Velocity Measurements using Email”, J. Instrum. Soc. Ind. 42(3), 172-174 (2012).
 
[33]  Singh G. K., “Control of Virtual Instrument using Wireless Technology”, Ph.D. Thesis, RTM Nagpur University, September 2012.
 
[34]  Gupta S. and John J., “Virtual Instrumentation Using Lab VIEW”, Tata McGraw-Hill Publishing Ltd, New Delhi (2005).
 
[35]  Grosso D. A. V. and Mader W. C., “Speed of Sound in Pure Water”, J. Acoust. Soc. Am. 52(5.2), 1942-1946 (1972).
 
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Article

Decision Based Median Filter Algorithm Using Resource Optimized FPGA to Extract Impulse Noise

1Research Scholar, Department of Technology, Shivaji University, Kolhapur

2Professor, Department of Technology, Shivaji University, Kolhapur


Journal of Embedded Systems. 2014, 2(1), 18-22
DOI: 10.12691/jes-2-1-4
Copyright © 2014 Science and Education Publishing

Cite this paper:
Rutuja N. Kulkarni, P.C. Bhaskar. Decision Based Median Filter Algorithm Using Resource Optimized FPGA to Extract Impulse Noise. Journal of Embedded Systems. 2014; 2(1):18-22. doi: 10.12691/jes-2-1-4.

Correspondence to: Rutuja  N. Kulkarni, Research Scholar, Department of Technology, Shivaji University, Kolhapur. Email: kulkarni.rutuja@gmail.com

Abstract

Median filter is a non-linear filter used in image processing for impulse noise removal. It finds its typical application in the situations where edges are to be preserved for higher level operations like segmentation, object recognition etc. This paper presents accurate and efficient noise detection and filtering algorithm for impulse noise removal. The algorithm includes two stages: noise detection followed by noise filtering. The proposed algorithm replaces the noisy pixel by clipping median value when other pixel values, 0’ s or 255’ s are present in the selected window and when all the pixel values are 0’ s and 255’ s then the noise pixel is replaced by mean value of all the elements present in the selected window. This median filter was designed, simulated and synthesized on the Xilinx family of FPGAs (XC3S500E of Spartan-3E). The VHDL was used to design the above 2-D median filter using ISE (Xilinx) tool & tested & compared for different grayscale images.

Keywords

References

[1]  Daggu Venkateshwar Rao, Shruti Patil, Naveen Anne Babu and V Muthukumar “Implementation and Evaluation of Image Processing Algorithms on Reconfigurable Architecture using C-based Hardware Descriptive Languages” International Journal of Theoretical and Applied Computer Sciences Volume 1 Number 1 (2006) pp. 9-34.
 
[2]  H. Hwang and R. A. Hadded, “Adaptive median filter: New algorithms and results,” IEEE Trans. Image Process., vol. 4, no. 4, pp. 499-502, Apr. 1995.
 
[3]  S. Zhang and M. A. Karim, “A new impulse detector for switching median filters,” IEEE Signal Process. Lett., vol. 9, no. 11, pp. 360-363, Nov. 2002.
 
[4]  P. E. Ng and K. K. Ma, “A switching median filter with boundary discriminative noise detection for extremely corrupted images,” IEEE Trans. Image Process., vol. 15, no. 6, pp. 1506-1516, Jun. 2006.
 
[5]  W. Zhou and Z. David, “Progressive switching median filter for the removal of impulse noise from highly corrupted images,” IEEE Trans On Circuits and Systems: Analog and Digital Signal Processing, vol. 46, no. 1, pp. 78-80, 1999.
 
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[6]  D. R. K. Brownrigg, “The weighted median filter,” Commun. ACM, vol. 27, no. 8, pp. 807-818, 1984.
 
[7]  S. Marshall, “New direct design method for weighted order statistic filters,” VISP, vol. 151, no. 1, pp. 1-8, February 2004.
 
[8]  M. C Hanumantharaju, M. Ravishankar, D. R Rameshbabu and S. B Satish “An Efficient VLSI Architecture for Adaptive Rank Order Filter for Image Noise Removal” International Journal of Information and Electronics Engineering, Vol. 1, No. 1, July 2011.
 
[9]  Tarek M. Bittibssi, Gouda I. Salama, Yehia Z. Mehaseb and Adel E. Henawy “Image Enhancement Algorithms using FPGA” International Journal of Computer Science & Communication Networks, Vol. 2 (4), 536-542.
 
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Article

A Novel System-on-Chip (SoC) Integration Open Core Protocol (OCP) Bus with Multiple Master & Slave Support

1Deparment of ETC, SIET, DHENKANAL,ODISHA

2Deparment of ELTCE, VSSUT, BURLA, ODISHA


Journal of Embedded Systems. 2014, 2(2), 23-27
DOI: 10.12691/jes-2-2-1
Copyright © 2014 Science and Education Publishing

Cite this paper:
Snigdharani Nath, Manas Ranjan Jena, Shilparani Panda. A Novel System-on-Chip (SoC) Integration Open Core Protocol (OCP) Bus with Multiple Master & Slave Support. Journal of Embedded Systems. 2014; 2(2):23-27. doi: 10.12691/jes-2-2-1.

Correspondence to: Manas  Ranjan Jena, Deparment of ELTCE, VSSUT, BURLA, ODISHA. Email: manas.synergy@gmail.com

Abstract

In this paper, we have designed a System-on-Chip (SoC) Integration with Open Core Protocol (OCP) both master and slave cores particularly in the burst and in the tag mode. The master core is responsible for initiating the communication on the bus. The slave core is the device that has been addressed by the master in order to establish the communication. Multiple OCP transfers can be linked into a burst transaction Cores such as DRAM controllers can supply the second related piece of data much faster than the first Bursts allow a target to know that there are more transfers coming, so it can pre-fetch. Tags allow out-of-order return of responses and out-of-order commit of write data. In IP core plug-and-play reuse, cores need to be coupled from one another using a clearly specified core interface protocol. The core must be portable from one SOC design to the next without integration rework. Taking advantage of the increasing density of IC process technologies remains extremely dependant on a formidable challenge. Adapting cores from chip design to chip design to make them fit with the rest of the system-on-a-chip (SOC) has become for a while a totally inefficient and unproductive methodology. Each time a core is to be integrated into a new system the system integrator is hampered by massive rework that reduces productivity.

Keywords

References

[1]  Jari Nurmi, “Processor design: System-on-chip computing for ASICS & FPGAS”, Springer 1st edition, 2007.
 
[2]  Sonics, Inc. Open Core Protocol Specification Reference Guide Version 2.0.
 
[3]  Wolf-Dietrich Weber “Enabling Reuse via an IP Core-centric Communications Protocol: Open Core Protocol.” Sonics, Inc.
 
[4]  Farzad Nekoogar & Faranak Nekoogar “From ASICS to SOCS:A practical approach”, Pearson Educaton, 2003.
 
[5]  Satoshi Komatsu, Shota Watanabe “Protocol Transducer Synthesis using Divide and Conquer approach” IEEE, 1-4244-0630-7/07-2007.
 
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[6]  Douglas J Smith, HDL Chip Design.
 
[7]  Chih-Wea Wang, Chi-Shao Lai, Chi-Feng Wu, Shih-Arn Hwang, and Ying-Hsi Lin “On-chip Interconnection Design and SoC Integration with OCP” IEEE 1-4244-1617-2/08-2008
 
[8]  Bhaskar, J.A, “VHDL Primer”, Pearson Education thirteenth edition-2004.
 
[9]  Clifford E. Cummings “Simulation and Synthesis Techniques for Asynchronous FIFO Design” Sunburst Design, Inc.
 
[10]  Carl Harmacture, Computer Architecture.
 
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Article

A Novel Dedicated Low Power 64 Bit Digital Comparator Using Cmos Logic

1Deparment of ETC, SIET, DHENKANAL,ODISHA

2Deparment of ELTCE, VSSUT, BURLA, ODISHA


Journal of Embedded Systems. 2014, 2(2), 28-31
DOI: 10.12691/jes-2-2-2
Copyright © 2014 Science and Education Publishing

Cite this paper:
Shilparani Panda, Asirbad Behera, Manas Ranjan Jena, Snigdharani Nath. A Novel Dedicated Low Power 64 Bit Digital Comparator Using Cmos Logic. Journal of Embedded Systems. 2014; 2(2):28-31. doi: 10.12691/jes-2-2-2.

Correspondence to: Manas  Ranjan Jena, Deparment of ELTCE, VSSUT, BURLA, ODISHA. Email: manas.synergy@gmail.com

Abstract

In this paper we have designed a novel dedicated low power 64 bit digital comparator. Magnitude comparison is one of the basic functions used for sorting in microprocessor, digital signal processing, so a high performance, effective magnitude comparator is required. The main objective of this paper is to provide new low power, area solution for Very Large Scale Integration (VLSI) designers. A Low Power 64-bit CMOS binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on power delay product. Modifications are done in existing 64-bit binary comparator design to improve the PDP of the circuit. Simulation of the proposed design is performed at 180 nm technology in Tanner EDA Tool.

Keywords

References

[1]  M. Morris Mano “Digital Design” (Pearson Education Asia. 3rd Ed, 2002).
 
[2]  Shun-Wen Cheng, “A High-Speed Magnitude Comparator with Small Transistor Count” in Proceedings of IEEE international conference ICECS, 1168-1171 Vol. 3, Dec 2003.
 
[3]  S. Kang and Y. Leblebici “CMOS Digital Integrated Circuit, Analysis and Design” (Tata McGraw-Hill, 3rd Ed, 2003).
 
[4]  H.M. Lam and C. Y. Tsui, “High performance single clock cycle CMOS comparators,” Electron. Lett. vol. 42, no. 2, pp. 75-77, Jan. 2006.
 
[5]  H.M. Lam and C. Y. Tsui, “A MUX based high performance single cycle CMOS comparator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 7, pp. 591-595, Jul. 2007.
 
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[6]  Y. Jiang, S. S. Sapatneker, and C. Bamji, “Technology mapping for high performancestatic CMOS and pass transistor logic designs,” IEEE Trans. VLSI Syst., vol. 9, pp. 577–589, Oct. 2001.
 
[7]  Chua-Chin Wang, C.-F. Wu, and K.-C. Tsai, “A 1.0 GHz 64-bit High-speed Comparator Using ANT Dynamic Logic with Two-Phase Clocking,” IEE Proceedings -Compurers and Digital Techniques, vol. 145, no. 6, pp. 433436, Nov. 1998.
 
[8]  A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design. Norwell, MA: Kluwer, 1995.
 
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Article

A Low Cost High Precision Virtual Instrumentation for Potentiometric Titration

1Department of Electronics, J. B. Science College, Wardha, India

2Department of Electronics, Nagpur university Campus, Nagpur, India


Journal of Embedded Systems. 2014, 2(2), 32-34
DOI: 10.12691/jes-2-2-3
Copyright © 2014 Science and Education Publishing

Cite this paper:
V. M. Ghodki, S. J. Sharma, S. Rajagopalan. A Low Cost High Precision Virtual Instrumentation for Potentiometric Titration. Journal of Embedded Systems. 2014; 2(2):32-34. doi: 10.12691/jes-2-2-3.

Correspondence to: V.  M. Ghodki, Department of Electronics, J. B. Science College, Wardha, India. Email: vilasghodki@rediffmail.com

Abstract

We propose a high precision personal computer (PC) based virtual instrumentation for potentiometric titration technique using Advantech USB 4711A data acquisition module. The entire titration including online data acquisition followed by immediate online analysis of data to get information about concentration of unknown sample is completed within a couple of seconds. The test setup is developed in our laboratory using Advantech’s data acquisition card, USB 4711A interfaced to the IBM compatible PC, operated under windows 7 operating system. A simple and inexpensive signal processing circuit is designed in our laboratory using off-the-shelf components, to amplify signal received from glass electrode. Powerful and effective data acquisition software VB.NET is used at back end as well as front end to accomplish data acquisition, parameter setting, file manipulation, control and synchronization of the other functions involved in the measurements. The control panel directly displays the strength of liquid under test at a given temperature.

Keywords

References

[1]  National Instruments LabVIEW, Measurements Manual, National Instruments: Austin, Texas, July 2000 ed.
 
[2]  Vyas N. S., “Condition monitoring Applications using Virtual Instrumentation”, 28th National Symposium on Instrumentation (NSI), Pantnagar (Uttaranchal), India (2003)
 
[3]  Vijaykumar P. N., “Virtual Instruments in Research”, 28th National Symposium on Instrumentation, Pantnagar, (Uttaranchal), India (2003).
 
[4]  G. W. Johnson, “LabVIEW Graphical Programming: Practical Applications in Instrumentation and Control, McGraw Hill New York, 1994.
 
[5]  Ghodki V. M., “Development of PC based Technique for Acoustic Measurements”, Ph. D. Thesis, RTM Nagpur University, March 2005.
 
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[6]  A. Economou, S. D. Bolis, C. E. Efstathio, G. J. Volikakis, Anal. Chim. Acta, 467, 179-188(2002).
 
[7]  J.K. Foreman and P.B. Stockwell, Automatic Chemical Analyasis, Ellis Horwood, 1975.
 
[8]  J.P.Walters, Analytical Chemistry, 67, 34A-35a (1995).
 
[9]  Rajagopalan S., Sharma S. J. and Ghodki V. M., “PC based Design of Single Pulse Sender/receiver Technique for Ultrasonic Velocity Measurements”, J. Pure & Appl. Ultason. 29, 143-145 (2007).
 
[10]  Rajagopalan S., Sharma S. J. and Ghodki V. M., “Design of PC based Sing-around System”, J. Instrum. Soc. Ind. 37 (4), 206-211 (2007).
 
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Article

Design of an Efficient Dedicated Low Power High Speed Full Adder

1Deparment of ETC, SIET, DHENKANAL, ODISHA, INDIA


Journal of Embedded Systems. 2014, 2(3), 35-38
DOI: 10.12691/jes-2-3-1
Copyright © 2014 Science and Education Publishing

Cite this paper:
Asirbad Behera, Manas Ranjan Jena, Abhinna Das, Narendra Kumar Pattnayak. Design of an Efficient Dedicated Low Power High Speed Full Adder. Journal of Embedded Systems. 2014; 2(3):35-38. doi: 10.12691/jes-2-3-1.

Correspondence to: Manas  Ranjan Jena, Deparment of ETC, SIET, DHENKANAL, ODISHA, INDIA. Email: manas.synergy@gmail.com

Abstract

In this paper, we have designed an efficient full adder with high speed & low power. As day by day more complex arithmetic circuits are presented, the power consumption becomes more important. Increasing demand for fast growing technologies in mobile electronic devices such as cellular phones, PDA’s and laptop computers requires the use of a low-power Full Adder in VLSI system. One way to reduce the power by reducing the power. However, decreasing power supply increases the circuit’s delay which is in contrast with high speed. So the power delay product (PDP) represents a trade-off between two compromising feature of power dissipitation and circuit delay. The new high speed high performance full adder is implemented by using CMOS technology. Simulation has been carried out on “MENTOGRAPHICS TOOLS” on 250 nm technology. Modification was done to optimize W/L ratio with different power supply. Results were compared with previously done single bit full adder circuit in terms of power, delay and power delay product (PDP).The results involves better performance compared to traditional adders.

Keywords

References

[1]  B.V.N Srivastav, Gummidipudi, “power efficient system design”, chapter 2.
 
[2]  A.M. Shams, T.K. Darwish, M.A. Bayoumi, “Performance analysis of low-power 1-bit CMOS Full Adder cells”, IEEE Transactions on VLSI Systems 10 (2002) 20-29.
 
[3]  Keivan Navi, Horialsadat Hossein, Reza Faghih, Mohammad hossein Moaiyeri, Ali Jalali, Omid kavehei, “full adder based on minority function and bridge style for nano scale”. The VLSI journal 44 the VLSI journal 44, 2011.
 
[4]  Mariano Aguirre-Hernandez and Monico Linares-Aranda, “CMOS Full-Adders for Efficient Arithmetic Applications”, IEEE Transactions on very large scale integration (vlsi) systems, vol. 19, no. 4, April 2011.
 
[5]  Xiongfei meng B.A.Sc., The University of British Columbia, 2004, “Decoupling capacitor design issues in 90nm cmos”, thesis, The University of British Columbia April 2006.
 
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[6]  Subodh wairya, Rajendra kumar Nagaria,Sudarsan Tiwari, New design methodologies for high speed mixed mode CMOS full adder circuit” International journal of vlsi design and communication system vol. 2 No. 2 June 2011
 
[7]  O.Kavehei, M.Rahimi Azghadi, K.Navi, A.P.Mirbaha, Design of robust and high-performance 1-bit CMOS Full Adder for nanometer design”, IEEE Comput. Soc. Annu. Symp. VLSIISVLSI08 Montpellier Fr. (2008) 10-15.
 
[8]  Ashkan Khatir1, Shaghayegh Abdolahzadegan 2, “high speed multiple valued logic full adder using carbon nano tube field effect transistor”, International Journal of VLSI design & Communication Systems (VLSICS) Vol. 2, No. 1, March 2011.
 
[9]  J.M.Rabaey, A.Chandrakasan, B.Nikolic, Digital Integrated Circuits, ADesign Perspective”, second ed., Prentice Hall, Englewood Cliffs, NJ, 2002.
 
Show Less References

Article

Studying the Impact of Scheduler Implementation on Task Jitter in Real-Time Resource-Constrained Embedded Systems

1Department of Electrical Engineering, College of Engineering and Islamic Architecture, Umm Al-Qura University, Makkah, KSA


Journal of Embedded Systems. 2014, 2(3), 39-52
DOI: 10.12691/jes-2-3-2
Copyright © 2014 Science and Education Publishing

Cite this paper:
Mouaaz Nahas. Studying the Impact of Scheduler Implementation on Task Jitter in Real-Time Resource-Constrained Embedded Systems. Journal of Embedded Systems. 2014; 2(3):39-52. doi: 10.12691/jes-2-3-2.

Correspondence to: Mouaaz  Nahas, Department of Electrical Engineering, College of Engineering and Islamic Architecture, Umm Al-Qura University, Makkah, KSA. Email: mmnahas@uqu.edu.sa

Abstract

Over recent decades, many studies have considered the development, assessment and refinement of scheduling algorithms for use in real-time embedded applications. Various studies have also considered the impact of variations in the interval between the executions of periodic tasks (i.e. jitter) on the behaviour of such systems. Despite interest in both of these areas, there has been comparatively little attention paid to the impact of scheduler implementation techniques on jitter behaviour. This is unfortunate because – as we demonstrate in the course of this paper – there is a ‘one-to-many’ mapping between scheduler algorithms and scheduler implementations, and even comparatively small changes in the scheduler implementation can have a significant impact on jitter behaviour. Throughout this paper, our focus is on implementations of a form of “cyclic executive” which is one of the simplest scheduling algorithms in widespread use. The results presented demonstrate that – even for this very simple scheduling algorithm – implementation decisions can have a significant impact on both jitter behaviour and on resource requirements. We would expect that the results obtained would also apply to more complicated algorithms: indeed, as the algorithms grow more complicated, we would expect that the number of implementation options would increase, with a corresponding increase in the jitter variation.

Keywords

References

[1]  M. Sanfridson, “Timing problems in distributed real-time computer control systems,” Mechatronics Lab, Dept. of Machine Design, Royal Inst. of Technology, Stockholm, 2000.
 
[2]  K.-J. Lin and A. Herkert, “Jitter control in time-triggered systems,” in System Sciences, 1996., Proceedings of the Twenty-Ninth Hawaii International Conference on ,, 1996, vol. 1, pp. 451-459.
 
[3]  P. Marti, J. M. Fuertes, G. Fohler, and K. Ramamritham, “Jitter compensation for real-time control systems,” in 22nd IEEE Real-Time Systems Symposium, 2001. (RTSS 2001). Proceedings, 2001, pp. 39-48.
 
[4]  T. Nolte, H. Hansson, and C. Norstrom, “Minimizing CAN response-time jitter by message manipulation,” in Eighth IEEE Real-Time and Embedded Technology and Applications Symposium, 2002. Proceedings, 2002, pp. 197-206.
 
[5]  M. Nahas and M. J. Pont, “Using XOR operations to reduce variations in the transmission time of CAN messages: A pilot study,” in Proceedings of the Second UK Embedded Forum, Birmingham, UK, 2005, pp. 4-17.
 
Show More References
[6]  M. Nahas, M. J. Pont, and M. Short, “Reducing message-length variations in resource-constrained embedded systems implemented using the Controller Area Network (CAN) protocol,” Journal of Systems Architecture, vol. 55, no. 5-6, pp. 344-354, May 2009.
 
[7]  F. Cottet and L. David, “A Solution to the Time Jitter Removal in Deadline Based Scheduling of Real-time Applications,” presented at the 5th IEEE Real-Time Technology and Applications Symposium-WIP, Vancouver, Canada, 1999, pp. 33-38.
 
[8]  A. J. Jerri, “The Shannon sampling theorem #8212; Its various extensions and applications: A tutorial review,” Proceedings of the IEEE, vol. 65, no. 11, pp. 1565-1596, Nov. 1977.
 
[9]  S. H. Hong, “Scheduling algorithm of data sampling times in the integrated communication and control systems,” IEEE Transactions on Control Systems Technology, vol. 3, no. 2, pp. 225-230, Jun. 1995.
 
[10]  A. Stothert and I. M. Macleod, “Effect of Timing Jitter on Distributed Computer Control System Performance,” in Proceedings of the 15th IFAC Workshop on Distributed Computer Control Systems (DCCS’98), 1998.
 
[11]  M. Nahas, M. Short, and M. J. Pont, “The impact of bit stuffing on the real-time performance of a distributed control system,” presented at the Proceeding of the 10th International CAN conference iCC, Rome, Italy, 2005, pp. 10-1-10-7.
 
[12]  T. P. Baker and A. Shaw, “The cyclic executive model and Ada,” Real-Time Syst, vol. 1, no. 1, pp. 7-25, Jun. 1989.
 
[13]  B. Koch, “The Theory of Task Scheduling in Real-Time Systems: Compilation and Systematization of the Main Results,” Studies Thesis, University of Hamburg, 1999.
 
[14]  M. J. Pont, Patterns for time-triggered embedded systems: building reliable applications with the 8051 family of microcontrollers. Harlow: Addison-Wesley, 2001.
 
[15]  S. K. Baruah, “The Non-preemptive Scheduling of Periodic Tasks upon Multiprocessors,” Real-Time Systems, vol. 32, no. 1-2, pp. 9-20, Feb. 2006.
 
[16]  C. Mwelwa, “Development and Assessment of a Tool to Support Pattern-Based Code Generation of Time-Triggered (TT) Embedded Systems,” PhD Thesis, University of Leicester, Leicester, UK, 2006.
 
[17]  T. Phatrapornnant and M. J. Pont, “Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling,” IEEE Transactions on Computers, vol. 55, no. 2, pp. 113-124, Feb. 2006.
 
[18]  M. J. Pont, S. Kurian, H. Wang, and T. Phatrapornnant, “Selecting an appropriate scheduler for use with time-triggered embedded systems.,” in Proceedings of the 12th European Conference on Pattern Languages of Programs (EuroPLoP ’2007), Irsee, Germany, 2007, pp. 595-618.
 
[19]  C. D. Locke, “Software architecture for hard real-time applications: Cyclic executives vs. fixed priority executives,” The Journal of Real-Time Systems, vol. 4, no. 1, pp. 37-53, Mar. 1992.
 
[20]  C. L. Liu and J. W. Layland, “Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment,” J. ACM, vol. 20, no. 1, pp. 46-61, Jan. 1973.
 
[21]  Y. Cho, S. Yoo, K. Choi, N.-E. Zergainoh, and A. A. Jerraya, “Scheduler implementation in MP SoC design,” in Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific, 2005, vol. 1, pp. 151-156 Vol. 1.
 
[22]  J. Y.-T. Leung and J. Whitehead, “On the complexity of fixed-priority scheduling of periodic, real-time tasks,” Performance Evaluation, vol. 2, no. 4, pp. 237-250, Dec. 1982.
 
[23]  A. K.-L. Mok, “Fundamental design problems of distributed systems for the hard-real-time environment,” Thesis, Massachusetts Institute of Technology, 1983.
 
[24]  G. C. Buttazzo, Hard real-time computing systems: predictable scheduling algorithms and applications. New York: Springer, 2005.
 
[25]  S. Key, M. J. Pon, and S. Edwards, “Implementing Low-cost TTCS Systems using Assembly Language.,” in Proceedings of the Eighth European conference on Pattern Languages of Programs (EuroPLoP 2003), Germany, 2003, pp. 667-690.
 
[26]  Z. H. Hughes and M. J. Pont, “Design and test of a task guardian for use in TTCS embedded systems,” in Proceedings of the UK Embedded Forum 2004, Birmingham, UK, 2004, pp. 16-25.
 
[27]  Z. M. Hughes and M. J. Pont, “Reducing the impact of task overruns in resource-constrained embedded systems in which a time-triggered software architecture is employed,” Transactions of the Institute of Measurement and Control, vol. 30, no. 5, pp. 427-450, Dec. 2008.
 
[28]  M. Nahas, M. J. Pont, and A. Jain, “Reducing task jitter in shared-clock embedded systems using CAN,” in Proceedings of the UK Embedded Forum 2004, Birmingham, UK, 2004, pp. 184-194.
 
[29]  M. Nahas, “Employing Two ‘Sandwich Delay’ Mechanisms to Enhance Predictability of Embedded Systems Which Use Time-Triggered Co-Operative Architectures,” Journal of Software Engineering and Applications, vol. 04, no. 07, pp. 417-425, 2011.
 
[30]  D. I. Katcher, H. Arakawa, and J. K. Strosnider, “Engineering and analysis of fixed priority schedulers,” IEEE Transactions on Software Engineering, vol. 19, no. 9, pp. 920-934, Sep. 1993.
 
[31]  J. Xu, “On inspection and verification of software with timing requirements,” IEEE Transactions on Software Engineering, vol. 29, no. 8, pp. 705-720, Aug. 2003.
 
[32]  G. S. Avrunin, J. C. Corbett, and L. K. Dillon, “Analyzing partially-implemented real-time systems,” IEEE Transactions on Software Engineering, vol. 24, no. 8, pp. 602-614, Aug. 1998.
 
[33]  Bosch, CAN Specification Version 2.0. Bosch, 1991.
 
[34]  T. Nolte, H. Hansson, C. Norström, and S. Punnekkat, “Using bit-stuffing distributions in CAN analysis,” presented at the IEEE Real-Time Embedded Systems Workshop, London, 2001.
 
[35]  Keil Software, “C166 Compiler, Optimizing 166/167 C Compiler and Library Reference, User Guide.” Keil Elektronik GmbH., and Keil Software, Inc., 1998.
 
[36]  National Instruments, “Low-Cost E Series Multifunction DAQ 12 or 16-Bit, 200 kS/s, 16 Analog Inputs.” [Online]. Available: http://www.ni.com/pdf/products/us/4daqsc202-204_ETCx2_212_213.pdf. [Accessed: 08-Mar-2014].
 
[37]  “LabVIEW System Design Software,” National Instruments. [Online]. Available: http://www.ni.com/labview/. [Accessed: 08-Mar-2014].
 
[38]  K. Baynes, C. Collins, E. Fiterman, B. Ganesh, P. Kohout, C. Smit, T. Zhang, and B. Jacob, “The performance and energy consumption of embedded real-time operating systems,” IEEE Transactions on Computers, vol. 52, no. 11, pp. 1454-1469, Nov. 2003.
 
[39]  M. J. Pont, S. Kurian, and R. Bautista-Quintero, “Meeting Real-Time Constraints Using ‘Sandwich Delays,’” in Transactions on Pattern Languages of Programming I, J. Noble and R. Johnson, Eds. Springer Berlin Heidelberg, 2009, pp. 94-102.
 
[40]  J. Xu and D. L. Parnas, “Priority Scheduling Versus Pre-Run-Time Scheduling,” Real-Time Systems, vol. 18, no. 1, pp. 7-23, Jan. 2000.
 
[41]  D. Ayavoo, M. J. Pont, M. Short, and S. Parker, “Two novel shared-clock scheduling algorithms for use with ‘Controller Area Network’ and related protocols,” Microprocessors and Microsystems, vol. 31, no. 5, pp. 326-334, Aug. 2007.
 
[42]  M. Nahas, “Estimating Message Latencies in Time-Triggered Shared-Clock Scheduling Protocols Built on CAN Network,” Journal of Embedded Systems, vol. 2, no. 1, pp. 1-10, 2014.
 
[43]  M. Nahas, “Developing a Novel Shared-Clock Scheduling Protocol for Highly-Predictable Distributed Real-Time Embedded Systems,” American Journal of Intelligent Systems, vol. 2, no. 5, pp. 118-128, Dec. 2012.
 
[44]  Texas Instruments, “74LS08 Datasheet.” [Online]. Available: http://www.cs.amherst.edu/~sfl<aplan/courses/spring-2002/cs14/74LS08-datasheet. pdf. [Accessed: 08-Mar-2014].
 
[45]  M. Farsi and M. B. M. Barbosa, CANopen implementation: applications to industrial networks. Baldock, Hertfordshire, England; Philadelphia, PA: Research Studies Press, 1999.
 
[46]  Infineon Technologies, “C167CR Derivatives: 16-Bit Single-chip Microcontroller; Microcontrollers. User’s manual V 3.1.” Mar-2000.
 
[47]  L. Hatton, “Programming Languages and Safety-Related Systems,” in Achievement and Assurance of Safety, F. Redmill and T. Anderson, Eds. Springer London, 1995, pp. 48-64.
 
[48]  J. A. de la Puente and J. Zamorano, “Execution-time Clocks and Ravenscar Kernels,” in Proceedings of the 12th International Workshop on Real-time Ada, New York, NY, USA, 2003, pp. 82-86.
 
Show Less References

Article

Low Cost Data Acquisition and Control System Based on Single Chip

1Depatrment of Electronics, RTM Nagpur university Nagpur-33 India

2Department of Physics RTM Nagpur University, Nagpu-33 India

3Department of Physics, Dr. Ambedkar college, Nagpu-10 India


Journal of Embedded Systems. 2014, 2(3), 53-57
DOI: 10.12691/jes-2-3-3
Copyright © 2014 Science and Education Publishing

Cite this paper:
Anup P. Bhat, S. J. Dhoble, K. G. Rewatkar. Low Cost Data Acquisition and Control System Based on Single Chip. Journal of Embedded Systems. 2014; 2(3):53-57. doi: 10.12691/jes-2-3-3.

Abstract

The advance technological, the processes monitoring are becoming more complex with increase in, efficient, analysis of process, number of parameters under data acquisition with single chip environment is increases . New generation data acquisition developments have been emerge with controlling and monitoring with microcontroller technology, which enables real-time data collection, analysis, logging and plotting of data. The requirements the demand of an improved, efficient and up- to-date data logger is increasing, with combination of a sensor, microcontroller, and a data storage device. Data loggers are provided with real time record and time of acquisition. In this paper, a data logger prototype is designed and tested for the specific application as pressure, temperature and vibration. The system works around the AT-MEGA-16 microcontroller. The system is designed and developed to measure temperature, vibration and pressure with accurate sensors and the result is stored in memory such as EEPROM for post process analysis. During the testing, it is verified that there is real time correct data acquire and stored in memory. Using a LCD display verified the current data storage. The focus of design is on portability and low power consumption in robust environment.

Keywords

References

[1]  Y. H. Shaikh, A. R. Khan, “Design and Development of Data Acquisition System for Labortary Experiment” Minor Research Project funded by UGC New Delhi Govt of India.
 
[2]  Ding Sheng, Fan Zhiguo and Sun Chuang. “Design of a 2D Scanning Information Acquisition System of Atmospheric Polarization”, Natural Science ,2011.
 
[3]  Li Xiuli. “Design of Data Acquisition and Transmission System Based on MSP430”, Mechanical Engineering and Automation, 2011.
 
[4]  Liu Xiaoqiu. “Social Demand Decide Development of Monolithic Circuit Control System” ,Industrial Control Computer, 2008.
 
[5]  Ai Yu. Research on “Solar Battery Data Acquisition System Based on microcontroller” Wuhan University of Technology, 2010.
 
Show More References
[6]  Shen Qiang, Yang Denghong and Li Dongguang. “ Research and Implementation of Ballistic Resolving Algorithm Based on MSP430”. Journal of Beijing Institute of Technology, 2011.
 
[7]  Li Jicheng, Gao Zhenjiang, Xiao Hongwei, “Design and Experiment on Dairy Cow Precise Feeding Equipment Based on MCU” ,Transactions of the Chinese Society of Agricultural Machinery, 2011.
 
[8]  Lian Xiangyu, Tang Liping and Zhao Zuyun. Research on “Dynamic Configured Control System for MCU Application” Journal of Donghua University (Natural Sciences), 2010.
 
[9]  Ding Baohua, Zhang Youzhong, Chen Jun and Meng Fanxi. Experimental Teaching Reforms and Practices of MCU Principle and Interface,Experimental Technology and Management, 2010.
 
[10]  Jiang Juan. Software Design of Data Acquisition Boards Based on MCU ,ournal of China Jiliang University, 2011.
 
[11]  R. Fensli, "A Wireless ECG System for Continuous Event Recording and Communication to a Clinical Alarm Station", Proc of the 26th Annual International Conference of the IEEE EMBS, 2004.
 
[12]  Muhammad Ali Mazidi and Janice Gillispe Mazidi, “The 16 bit microcontroller and embedded systems”, Pearson education ltd., India, 2007.
 
[13]  Ziad Salem, Ismail Al Kamal, Alaa Al Bashar “A Novel Design of an Industrial Data Acquisition System”, Proc. of Int. Conf. on Inf. And Comm. Tech, ICTTA 2006.
 
[14]  S. Thanee S. Somkuarnpanit and K. Saetang, “FPGA-Based Multi Protocol Data Acquisition System with High Speed USB Interface” Proceedings of the international Multi Conference of Engineers and Computer Scientists 2010 Vol II, IMCES 2010, Hong Kong.
 
[15]  P. Asimakopoulos, G. Kaltsas and A. G. Nassiopoulou, “A microcontroller- based interface circuit for data acquisition and control of a micromechanical thermal flow sensor” Institute of Physics Publishing Journal of Physics: Conference Series 10 (2005).
 
[16]  A. J. Thompson, J. L. Bahr , “Low power data logger”, proceedings of conference department of physics, university of Otego, Dunedin2012.
 
[17]  Singh, N. Monoranjan, Sarma, K. C., 2009 “Low Cost PC Based Real Time Data Logging System Using PCs Parallel Port For Slowly Varying Signals”, Proceedings of 54th Annual Technical Session of Assam Science Society.
 
Show Less References

Article

Dependability Investigation of Wireless Short Range Embedded Systems: Hardware Platform Oriented Approach

1Embedded Systems Department, LACS Laboratory, Central Electronic Engineering School ECE- Paris, France

2Electrical Engineering, Mathematics and Computer Science Faculty, University of Twente, Netherlands


Journal of Embedded Systems. 2015, 3(1), 1-10
DOI: 10.12691/jes-3-1-1
Copyright © 2015 Science and Education Publishing

Cite this paper:
B. Senouci, H.G. Kerkhoff, M.J. Bentum, A.J Annema. Dependability Investigation of Wireless Short Range Embedded Systems: Hardware Platform Oriented Approach. Journal of Embedded Systems. 2015; 3(1):1-10. doi: 10.12691/jes-3-1-1.

Correspondence to: B.  Senouci, Embedded Systems Department, LACS Laboratory, Central Electronic Engineering School ECE- Paris, France. Email: senouci@ece.fr

Abstract

A new direction in short-range wireless applications has appeared in the form of high-speed data communication devices for distances of hundreds meters. Behind these embedded applications, a complex heterogeneous architecture is built. Moreover, these short range communications are introduced into critical applications, where the dependability/reliability is mandatory. Thus, dependability concerns around reliability evaluation become a major challenge in these systems, and pose several questions to answer. Obviously, in such systems, the attribute reliability has to be investigated for various components and at different abstraction levels. In this paper, we discuss the investigation of dependability in wireless short range systems. We present a hardware platform for wireless system dependability analysis as an alternative for the time consuming simulation techniques. The platform is built using several instances of one of the commercial FPGA platforms available on the market place. We describe the different steps of building the wireless hardware platform for short range systems dependability analysis. Then, we show how this HW platform based dependability investigation framework can be a very interactive approach. Based on this platform we introduce a new methodology and a flow to investigate the different parts of system dependability at different abstraction levels. The benefits to use the proposed framework are three fold: first, it takes care of the whole system (HW/SW -digital part, mixed RF part, and wireless part); Second, the hardware platform enables to explore the application’s reliability under real environmental conditions taking into account the effect of the environment threats on the system; And last, the wireless platform built for dependability investigation present a fast investigation approach in comparison with the time consuming co-simulation technique.

Keywords

References

[1]  A.Sangiovanni-Vincentelli and all “Benefits and Challenges for Platform-Based Design,” Design Automation Conference (DAC), 2004, pp. 409-414.
 
[2]  Avizienis, A; Laprie, J.-C.; Randell, B.; Landwehr, C. “Basic concepts and taxonomy of dependable and secure computing” IEEE Transactions on Dependable and Secure Computing, Issue Date: Jan.-March 2004, Volume: 1 Issue:1 On page(s): 11-33.
 
[3]  H.G Kerkhoff, X.Zhang “Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor” Proceedings of the 2010 Fifth IEEE International Symposium on Electronic Design, Test & Application, Pages: 270-275.
 
[4]  R.Mariani, S.Ulmiano “A Platform-Based Technology for Fault-Robust SoC Design” Design and Reuse SoC conference 2007.
 
[5]  http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion
 
Show More References
[6]  Alan Bensky “Short-range wireless communication: Fundamental of RF system Design and Application” 2005.
 
[7]  Functional safety and IEC 61508, September 2005.
 
[8]  Francis M.David, and all “Improving Dependability by Revisiting Operating System Design” HotDep'07: Proceedings of the 3rd workshop on on Hot Topics in System Dependability (2007).
 
[9]  Edmond, Gupta, Siewiorek, Brennan “ASSURE: automated design for dependability," pp.555-560, 27th ACM/IEEE Design Automation Conference (DAC '90).
 
[10]  Riccardo Mariani and all “Applying IEC 61508 to Integrated Circuits” Volume 6, Number 2, 2007.
 
[11]  Arnaud Albinet, Jean Arlat, Jean-Charles Fabre “Chapter 14. Benchmarking the Impact of Faulty Drivers: Application to the Linux Kernel” Dependability Benchmarking for Computer Systems Published Online: 7 JAN 2008.
 
[12]  Andreas Bernauer and all ‘An Architecture for Runtime Evaluation of SoC Reliability’ In INFORMATIK 2006 - Informatik für Menschen, Lecture Notes in Informatics, Köllen Verlag, vol. P-93 of GI-Edition.
 
[13]  B.Senouci, A.Bouchhima, F.Rousseau, F.Petrot, A.Jerraya, “Fast prototyping Methodology of Distributed SoC applications on a Multiprocessor Hardware Platform", IEEE Distributed Systems Online, vol. 8, no. 5, 2007, art. No. 0705-o5002.
 
[14]  http://www.freertos.org/.
 
[15]  http://www.xilinx.com/.
 
[16]  Stefan Lindenmeier, Anestis Terzis “A DSSS-Based Wireless Short Range Data-Link Original Research Article AEU” - International Journal of Electronics and Communications, Volume 57, Issue 3, 2003, Pages 161-167.
 
[17]  Clive Pygott, Stephen P. Wilson “Justifying reliability claims for a fault-detecting parallel architecture” Journal of Systems Architecture, Volume 43, Issue 10, 1997, Pages 735 751.
 
[18]  Nicola Mazzocca, Stefano Russo, Valeria Vittorini “Formal methods integration for the specification of dependable distributed systems” Journal of Systems Architecture, Volume 43, Issue 10, 1997, Pages 671-685.
 
[19]  K. Masselos, A. Pelkonen, M. Cupak, S. Blionas “Realization of wireless multimedia communication systems on reconfigurable platforms” Journal of Systems Architecture, Volume 49, Issues 4–6, September 2003, Pages 155-175.
 
[20]  K.G.Padmasine, S.Muruganand “System on Chip (PSoC) Control for High Current Magnet Power Supply” Journal of Embedded Systems, 2014, Vol. 2, No. 1,11-14.
 
[21]  Dadashi, M.; Rashid, L.; Pattabiraman, K.; Gopalakrishnan, S., “Hardware-Software Integrated Diagnosis for Intermittent Hardware Faults,” Dependable Systems and Networks (DSN), 2014 44th Annual IEEE/IFIP International Conference on, vol., no., pp.363, 374, 23-26 June 2014.
 
Show Less References