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Article

Decision Based Median Filter Algorithm Using Resource Optimized FPGA to Extract Impulse Noise

1Research Scholar, Department of Technology, Shivaji University, Kolhapur

2Professor, Department of Technology, Shivaji University, Kolhapur


Journal of Embedded Systems. 2014, 2(1), 18-22
DOI: 10.12691/jes-2-1-4
Copyright © 2014 Science and Education Publishing

Cite this paper:
Rutuja N. Kulkarni, P.C. Bhaskar. Decision Based Median Filter Algorithm Using Resource Optimized FPGA to Extract Impulse Noise. Journal of Embedded Systems. 2014; 2(1):18-22. doi: 10.12691/jes-2-1-4.

Correspondence to: Rutuja  N. Kulkarni, Research Scholar, Department of Technology, Shivaji University, Kolhapur. Email: kulkarni.rutuja@gmail.com

Abstract

Median filter is a non-linear filter used in image processing for impulse noise removal. It finds its typical application in the situations where edges are to be preserved for higher level operations like segmentation, object recognition etc. This paper presents accurate and efficient noise detection and filtering algorithm for impulse noise removal. The algorithm includes two stages: noise detection followed by noise filtering. The proposed algorithm replaces the noisy pixel by clipping median value when other pixel values, 0’ s or 255’ s are present in the selected window and when all the pixel values are 0’ s and 255’ s then the noise pixel is replaced by mean value of all the elements present in the selected window. This median filter was designed, simulated and synthesized on the Xilinx family of FPGAs (XC3S500E of Spartan-3E). The VHDL was used to design the above 2-D median filter using ISE (Xilinx) tool & tested & compared for different grayscale images.

Keywords

References

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[8]  M. C Hanumantharaju, M. Ravishankar, D. R Rameshbabu and S. B Satish “An Efficient VLSI Architecture for Adaptive Rank Order Filter for Image Noise Removal” International Journal of Information and Electronics Engineering, Vol. 1, No. 1, July 2011.
 
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Article

Design of Embedded Sing-around System for Ultrasonic Velocity Measurements in Liquids

1Department of Electronics, RTM Nagpur University, Nagpur, India

2Department of Electronics, Anand Niketan College, Warora, India

3Department of Electronics, J. B. Science College, Wardha, India


Journal of Embedded Systems. 2014, 2(1), 15-17
DOI: 10.12691/jes-2-1-3
Copyright © 2014 Science and Education Publishing

Cite this paper:
S. J. Sharma, A. C. Balharpure, A. S. Pande, S. U. Dubey, G. K. Singh, V. M. Ghodki, S. Rajagopalan. Design of Embedded Sing-around System for Ultrasonic Velocity Measurements in Liquids. Journal of Embedded Systems. 2014; 2(1):15-17. doi: 10.12691/jes-2-1-3.

Correspondence to: S.  J. Sharma, Department of Electronics, RTM Nagpur University, Nagpur, India. Email: sharmasat@gmail.com

Abstract

Among the pulse techniques in ultrasonics, sing around technique is widely used for measurements of ultrasonic velocity in liquids and solids. It is simple, versatile and highly accurate for absolute and relative ultrasonic velocity measurements. In the present work, an embedded sing around system, at operating frequency of 2 MHz, is designed around PIC 18F4550 microcontroller. Pulser and receiver circuits have been designed using locally available electronic components. Necessary controls have been dumped or embedded as software in the microcontroller to add intelligence to the sing around system. The designed system is compact, stand-alone, reliable, accurate and portable with onboard display of the ultrasonic velocity of propagation in the sample under study. Ultrasonic velocity measurements have been carried out in standard liquids and found to be in well agreement with the values reported in the literature.

Keywords

References

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Article

System on Chip (PSoC) Control for High Current Magnet Power Supply

1Department of Electronics & Instrumentation, Bharathiar University, Coimbatore


Journal of Embedded Systems. 2014, 2(1), 11-14
DOI: 10.12691/jes-2-1-2
Copyright © 2014 Science and Education Publishing

Cite this paper:
K.G. Padmasine, S. Muruganand. System on Chip (PSoC) Control for High Current Magnet Power Supply. Journal of Embedded Systems. 2014; 2(1):11-14. doi: 10.12691/jes-2-1-2.

Correspondence to: K.G.  Padmasine, Department of Electronics & Instrumentation, Bharathiar University, Coimbatore. Email: padmasinechandra@gmail.com

Abstract

This paper describes a high current magnet power supply control through a Programmable System on Chip (PSoC) based embedded design and its menu driven control program written in Virtual instrument program. This design supports a wider dynamic range of current from 0 to 120 amperes in steps of 0.1 amps to the magnet power supply. It also has the fine tuning facility of current in the range of 0.01 amps to the magnet. In the existing BRUKER make B-CN-120 model power supply a programmable port has been implemented through which the PSoC embedded design interact via PCs USB port configured through Lab VIEW program resides in the PC. The successful PSoC design implementation simplifies the automation of BRUKER Magnet power supply.

Keywords

References

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[[4]  Cypress semiconductor.
 
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Article

Estimating Message Latencies in Time-Triggered Shared-Clock Scheduling Protocols Built on CAN Network

1Department of Electrical Engineering, College of Engineering and Islamic Architecture, Umm Al-Qura University, Makkah, KSA


Journal of Embedded Systems. 2014, 2(1), 1-10
DOI: 10.12691/jes-2-1-1
Copyright © 2014 Science and Education Publishing

Cite this paper:
Mouaaz Nahas. Estimating Message Latencies in Time-Triggered Shared-Clock Scheduling Protocols Built on CAN Network. Journal of Embedded Systems. 2014; 2(1):1-10. doi: 10.12691/jes-2-1-1.

Correspondence to: Mouaaz  Nahas, Department of Electrical Engineering, College of Engineering and Islamic Architecture, Umm Al-Qura University, Makkah, KSA. Email: mmnahas@uqu.edu.sa

Abstract

The Controller Area Network (CAN) is an event-triggered protocol that is widely used in distributed real-time embedded systems. It has been demonstrated that a “Shared-Clock” (S-C) scheduling protocol can be used on top of CAN hardware to implement time-triggered network operations. Previous work in this area has led to the development of five different time-triggered S-C scheduling protocols referred to as: TTC-SCC1, TTC-SCC2, TTC-SCC3, TTC-SCC4 and TTC-SCC5 schedulers. This paper develops mathematical models for assessing message latencies between all communicating nodes in the different S-C scheduling protocols. In particular, the paper provides mathematical equations for estimating Master-to-Slave, Slave-to-Master, and Slave-to-Slave message latencies in all five schedulers. The paper then presents a small case study to allow a practical comparison of the communication behavior in the various S-C schedulers considered. The results show that the communication behavior, especially Slave-to-Slave message delays, can be improved significantly when TTC-SCC3, TTC-SCC4 and TTC-SCC5 scheduler implementations are used. The results also show that even a small selection of S-C scheduler implementations demonstrates a wide range of different patterns of behavior. It is therefore suggested that selection of the most appropriate scheduler will largely depend on requirements of the application for which the scheduler is intended.

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References

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