Journal of Embedded Systems
ISSN (Print): 2376-7987 ISSN (Online): 2376-7979 Website: http://www.sciepub.com/journal/jes Editor-in-chief: Naima kaabouch
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Journal of Embedded Systems. 2014, 2(1), 18-22
DOI: 10.12691/jes-2-1-4
Open AccessArticle

Decision Based Median Filter Algorithm Using Resource Optimized FPGA to Extract Impulse Noise

Rutuja N. Kulkarni1, and P.C. Bhaskar2

1Research Scholar, Department of Technology, Shivaji University, Kolhapur

2Professor, Department of Technology, Shivaji University, Kolhapur

Pub. Date: March 22, 2014

Cite this paper:
Rutuja N. Kulkarni and P.C. Bhaskar. Decision Based Median Filter Algorithm Using Resource Optimized FPGA to Extract Impulse Noise. Journal of Embedded Systems. 2014; 2(1):18-22. doi: 10.12691/jes-2-1-4

Abstract

Median filter is a non-linear filter used in image processing for impulse noise removal. It finds its typical application in the situations where edges are to be preserved for higher level operations like segmentation, object recognition etc. This paper presents accurate and efficient noise detection and filtering algorithm for impulse noise removal. The algorithm includes two stages: noise detection followed by noise filtering. The proposed algorithm replaces the noisy pixel by clipping median value when other pixel values, 0’ s or 255’ s are present in the selected window and when all the pixel values are 0’ s and 255’ s then the noise pixel is replaced by mean value of all the elements present in the selected window. This median filter was designed, simulated and synthesized on the Xilinx family of FPGAs (XC3S500E of Spartan-3E). The VHDL was used to design the above 2-D median filter using ISE (Xilinx) tool & tested & compared for different grayscale images.

Keywords:
impulse median filter PSNR salt & pepper FPGA

Creative CommonsThis work is licensed under a Creative Commons Attribution 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/

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