American Journal of Electrical and Electronic Engineering
ISSN (Print): 2328-7365 ISSN (Online): 2328-7357 Website: http://www.sciepub.com/journal/ajeee Editor-in-chief: Naima kaabouch
Open Access
Journal Browser
Go
American Journal of Electrical and Electronic Engineering. 2014, 2(4), 133-136
DOI: 10.12691/ajeee-2-4-2
Open AccessReview Article

Review of Leakage Power Reduction in CMOS Circuits

Khushboo Kumari1, Arun Agarwal2, , Jayvrat1 and Kabita Agarwal3

1B.Tech Student, Department of Electronics & Communication Engineering, Institute of Technical Education and Research, Siksha ‘O’ Anusandhan University, Khandagiri Square, Bhubaneswar, India

2Department of Electronics & Communication Engineering, Institute of Technical Education and Research, Siksha ‘O’ Anusandhan University, Khandagiri Square, Bhubaneswar, India

3Department Electronics & Telecommunication Engineering, CV Raman College of Engineering, Bhubaneswar, India

Pub. Date: August 29, 2014

Cite this paper:
Khushboo Kumari, Arun Agarwal, Jayvrat and Kabita Agarwal. Review of Leakage Power Reduction in CMOS Circuits. American Journal of Electrical and Electronic Engineering. 2014; 2(4):133-136. doi: 10.12691/ajeee-2-4-2

Abstract

Recent Technological advances in Wireless Communication has shown the convergence of terminals and networks that support multimedia and real-time applications. This obviously puts an immense pressure on battery of any mobile device. The CMOS has been the leading technology in today’s world of mobile communication due to its low power consumption. Reduction of leakage power in CMOS has been the research interest for the last couple of years. In CMOS integrated circuit design there is an important trade-off between technology scaling and static power consumption. In today’s CMOS technology the leakage power consumption plays a significant role. As we approaching to nano-scale design the total chip power consumption becomes dependent on leakage power. Increasing the battery life in mobile wireless communication and mobile computing and similar other applications is the topic of research now-a days... Further, since the leakage of battery exists even when devices are in idle state makes leakage power loss most critical in CMOS VLSI circuits. Many techniques have been evolved to tackle the problem and its still in progress. This paper mainly focuses on the review of various works done in this field till today’s date. Further a review of recent work done on a new technique LSSR (Lector Stack State Retention Technique) is discussed in the paper.

Keywords:
CMOS Leakage power VLSI circuits multimedia applications Static power Nano Scale LSSR

Creative CommonsThis work is licensed under a Creative Commons Attribution 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/

References:

[1]  Praveen Kumar, Pradeep SR, Pratibha SR, “LSSR: LECTOR Stacked State Retention Technique a novel leakage reduction and state retention technique in low power VLSI design,” IJERT, vol. 2, pp. 1-4, October 2013.
 
[2]  Velicheti Swetha, S.Rjeshwari, ”Design and Power Optimization of MT-CMOS circuits using power gating techniques,” IJAREEIE, vol. 2, August 2013.
 
[3]  Vinay Kumar Madasu, B Kedharnath, “Leakage power reducing by using sleep method,” IJECS, vol.2, pp. 2842-2847, September 2013.
 
[4]  Hina malviya, Sudha Nayar, “A new approach for Leakage Power Reduction Techniques in Deep Submicron Technologies in cmos circuit for vlsi applications .” International Journal of Advanced Research in Computer Science and Software Engineering, Volume 3, Issue 5, May 2013.
 
[5]  B.Dilip, P.Surya Prasad and R.S.G. Bhavani, “Leakage power reduction in CMOS circuits using leakage control transistor technique in nanosacle technology,” IJESS, vol. 2, 2012.
 
[6]  Dhananjay E. Upasani, Sandip B. Shrote, “Standby leakage reduction in nanoscale CMOS VLSI circuits,” International Journal on computer applications, vol. 7, September 2010.
 
[7]  Jun Seomun and youngsoo Shin, “Design and optimization of power –gated circuits with autonomous data retention,”IEEE transactions on VLSI system, vol. 19, no. 2, February 2011.
 
[8]  Narender Hanchateand and Nagaranjan Ranganathan, “LECTOR: A technique for leakage reduction in CMOS circuits,”IEEE transactions on VLSI systems, vol. 2, no. 2, pp. 196-200, Februrary 2004.
 
[9]  K.Flautner, S.Reinhardt, T.Mudge, “Automatic performance setting for dynamic voltage scaling,”7th International Conference on Mobile Computing and Networking, Rome, Italy, 2001.
 
[10]  Gu, R.X and M.I Elmasry, “Power dissipation analysis and optimization of deep sub-micron CMOS digital circuits,”IEEE journal of solid-state circuits, vol. 31, pp. 707-713, 1996.
 
[11]  S.H Kim and V.J. Mooney, “Sleepy Keeper: A new approach to low leakage power VLSI design,” IFIP, pp. 367-372, 2006.
 
[12]  Kyung Ki Kim, Yong-Binki, “Optimal body biasing for minimum leakage power in standby mode,”IEEE International Symposium on Circuits and Systems, pp. 27-30, May 2007.
 
[13]  J.Kao, A. Chandrakasan and D.Antoniadis, “Transistor sizing issues and tool for multi-threshold CMOS technology,” in proc. IEEE Design Automation Conf., pp.495-500, 1997.
 
[14]  Amerasekera and F. N. Najm, “Failure Mechanisms in Semiconductor Devices,”Wiley& Sons, 1998.
 
[15]  Chang-woo Kang and Massoud Pedram, “Technology Mapping for Low Leakage Power and High Speed with Hot Carrier Effect Consideration”, Design Automation Conference, Proceedings of the ASP-DAC , pp. 203-208, 2003.
 
[16]  Eitan N. Shauly, “CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations”, J. Low Power Electron. Appl. 2012, pp. 1-29.
 
[17]  Z. Chen, M. Johnson, L. Wei and K. Roy, “Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks”, In ISLPED, pp. 239-244, Aug., 1998.
 
[18]  K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, “Leakage Current Mechanisms and Leakage ReductionTechniques in Deep-Submicrometer CMOS Circuits”, In Proc. IEEE, vol. 91, pp. 305-327, Feb., 2003.
 
[19]  M. Johnson, D. Somasekhar, L.-Y.Chiou, and K. Roy, “Leakage control with efficient use of transistor stacks in single threshold CMOS,” IEEE Trans. VLSI Systems., vol. 10, no. 1, pp. 1-5, Feb. 2002.
 
[20]  S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS,” IEEE J. Solid-State Circuits, vol. 30, pp. 847-854, Aug. 1995.
 
[21]  Steven Keeping, “Design techniques for extending Li-ion battery life”, November 19, 2013.
 
[22]  Ken Bigelow, “Inside Computer Logic Gates”.
 
[23]  Se Hun Kim and Vincent J. Mooney III , “Sleepy Keeper : a New Approach to Low-Leakage Power VLSI Design”, in VLSI SOC conference 2006, PP. 367-372.
 
[24]  N. Hanchate and N. Ranganathan,” Lector: A technique for leakage reduction in CMOS circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol. 12, no. 2, pp. 196-205, February 2004.