American Journal of Electrical and Electronic Engineering
ISSN (Print): 2328-7365 ISSN (Online): 2328-7357 Website: http://www.sciepub.com/journal/ajeee Editor-in-chief: Naima kaabouch
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American Journal of Electrical and Electronic Engineering. 2020, 8(4), 120-124
DOI: 10.12691/ajeee-8-4-4
Open AccessLetter To Editor

CMOS Voltage-Controlled Negative Resistance Realization

Soumya Mourya1 and Raj Senani1,

1Department of Electronics and Communication Engineering, Netaji Subhash University of Technology (formerly, NSIT), Sector 3, Dwarka, New-Delhi 110078, India

Pub. Date: September 10, 2020

Cite this paper:
Soumya Mourya and Raj Senani. CMOS Voltage-Controlled Negative Resistance Realization. American Journal of Electrical and Electronic Engineering. 2020; 8(4):120-124. doi: 10.12691/ajeee-8-4-4

Abstract

In this communication, a new CMOS circuit configuration is proposed to realize a voltage-controlled negative resistance (VCNR) which has been implemented using only eight MOS transistors- all working in the saturation region. The value of the realized negative resistance is controlled by two identical and opposite external DC voltages. The workability of the proposed circuit has been confirmed by Cadence Virtuoso simulations and some sample results have been given. The proposed VCNR circuit has been shown to exhibit good linearity, has good variable negative resistance range from -1.05kΩ and -300Ω and offers a good operational frequency range up to around 100 MHz with total power dissipation between 0.5mW- 8.73mW only.

Keywords:
JFET MOSFET CMOS voltage-controlled resistance voltage-controlled negative resistance

Creative CommonsThis work is licensed under a Creative Commons Attribution 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/

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